Pentium® III Processor for the PGA370
Socket at 500 MHz to 1.13 GHz
Datasheet Revision 8
Product Features
The Pentium® III processor is designed for high-performance desktops and for workstations and
servers. It is binary compatible with previous Intel Architecture processors. The Pentium III processor
provides great performance for applications running on advanced operating systems such as Windows*
98, Windows NT and UNIX*. This is achieved by integrating the best attributes of Intel processors—
the dynamic execution, Dual Independent Bus architecture plus Intel MMX™ technology and Internet
Streaming SIMD Extentions— bringing a new level of performance for systems buyers. The Pentium
III processor is scaleable to two processors in a multiprocessor system and extends the power of the
Pentium® II processor with performance headroom for business media, communication and internet
capabilities. Systems based on Pentium III processors also include the latest features to simplify system
management and lower the cost of ownership for large and small business environments. The Pentium
III processor offers great performance for today’s and tomorrow’s applications.
FC-PGA370 Package
Available in 1.13 GHz, 1B GHz, 933, 866,
800EB, 733, 667, 600EB, and 533EB MHz
for a 133 MHz system bus
Available in 1.10 GHz, 1 GHz, 900, 850,
800, 750, 700, 650, 600E, 550E, and 500E
MHz for a 100 MHz system bus
System bus frequency at 100 MHz and
133 MHz (“E” denotes support for
Advanced Transfer Cache and Advanced
system buffering; “B” denotes support for a
133 MHz system bus where both bus
frequencies are available for order per each
given core frequency; See Table 1 for a
summary of features for each line item.)
Available in versions that incorporate
256-KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC))
Dual Independent Bus (DIB) architecture:
Separate dedicated external System Bus and
dedicated internal high-speed cache bus
Internet Streaming SIMD Extensions for
enhanced video, sound and 3D performance
Binary compatible with applications running
on previous members of the Intel
microprocessor line
Dynamic execution micro architecture
Intel Processor Serial Number
Power Management capabilities
—System Management mode
—Multiple low-power states
Optimized for 32-bit applications running on
advanced 32-bit operating systems
Flip Chip Pin Grid Array (FC-PGA/FC-PGA2)
packaging technology; FC-PGA/FC-PGA2
processors deliver high performance with
improved handling protection and socketability
Integrated high performance 16-KB instruction
and 16-KB data, nonblocking, level one cache
256-KB Integrated Full Speed level two cache
allows for low latency on read/store operations
Double Quad Word Wide (256 bit) cache data
bus provides extremely high throughput on
read/store operations.
8-way cache associativity provides improved
cache hit rate on reads/store operations.
Error-correcting code for System Bus data
Enables systems which are scaleable for up to
two processors
June 2001
Document Number: 245264-08
Datasheet
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifcations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium II, Pentium III, Pentium Pro, Celeron and Intel387 are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2001
Datasheet 3
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Contents
1.0 Introduction ..................................................................................................................8
1.1 Terminology...........................................................................................................9
1.1.1 Package and Processor Terminology ......................................................9
1.1.2 Processor Naming Convention...............................................................10
1.2 Related Documents.............................................................................................11
2.0 Electrical Specifications........................................................................................13
2.1 Processor System Bus and VREF........................................................................13
2.2 Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................16
2.2.4 HALT/Grant Snoop State—State 4 ........................................................16
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................17
2.2.7 Clock Control..........................................................................................17
2.3 Power and Ground Pins ......................................................................................17
2.3.1 Phase Lock Loop (PLL) Power...............................................................18
2.4 Decoupling Guidelines .......................................................................................19
2.4.1 Processor VCCCORE and AGTL+ (AGTL) Decoupling ...........................19
2.5 Processor System Bus Clock and Processor Clocking .......................................19
2.5.1 Mixing Processors of Different Frequencies...........................................20
2.6 Voltage Identification...........................................................................................20
2.7 Processor System Bus Unused Pins...................................................................22
2.8 Processor System Bus Signal Groups ................................................................22
2.8.1 Asynchronous vs. Synchronous for System Bus Signals .......................24
2.8.2 System Bus Frequency Select Signals (BSEL[1:0]) ...............................25
2.9 Maximum Ratings................................................................................................26
2.10 Processor DC Specifications...............................................................................27
2.10.1 ICC Slew Rate Specifications.................................................................33
2.11 AGTL / AGTL+ System Bus Specifications .........................................................36
2.12 System Bus AC Specifications ............................................................................37
2.12.1 I/O Buffer Model .....................................................................................37
3.0 Signal Quality Specifications..............................................................................46
3.1 BCLK/BCLK# and PICCLK Signal Quality Specifications and Measurement
Guidelines ...........................................................................................................46
3.2 AGTL+ / AGTL Signal Quality Specifications and Measurement Guidelines ......47
3.3 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................48
3.3.1 Overshoot/Undershoot Guidelines .........................................................48
3.3.2 Overshoot/Undershoot Magnitude .........................................................49
3.3.3 Overshoot/Undershoot Pulse Duration...................................................49
3.3.4 Activity Factor .........................................................................................49
3.3.5 Reading Overshoot/Undershoot Specification Tables............................50
3.3.6 Determining if a System Meets the Overshoot/Undershoot
Specifications .........................................................................................51
3.4 Non-AGTL+ (Non-AGTL) Signal Quality Specifications and Measurement
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
4 Datasheet
Guidelines ...........................................................................................................54
3.4.1 Overshoot/Undershoot Guidelines .........................................................54
3.4.2 Ringback Specification...........................................................................55
3.4.3 Settling Limit Guideline ..........................................................................55
4.0 Thermal Specifications and Design Considerations.................................56
4.1 Thermal Specifications........................................................................................56
4.2 Processor Die Area .............................................................................................57
4.3 Thermal Diode.....................................................................................................58
5.0 Mechanical Specifications ..................................................................................60
5.1 FC-PGA Mechanical Specifications ....................................................................60
5.1.1 FC-PGA2 Mechanical Specifications .....................................................63
5.2 Processor Markings ............................................................................................65
5.2.1 Processor Markings for FC-PGA2..........................................................65
5.3 Recommended Mechanical Keep-Out Zones .....................................................66
5.4 Processor Signal Listing......................................................................................67
6.0 Boxed Processor Specifications .......................................................................80
6.1 Mechanical Specifications for the Boxed Intel® Pentium® III Processor..............80
6.1.1 Boxed Processor Thermal Cooling Solution Dimensions.......................80
6.1.2 Boxed Processor Heatsink Weight.........................................................82
6.1.3 Boxed Processor Thermal Cooling Solution Clip ...................................82
6.2 Thermal Specifications........................................................................................82
6.2.1 Boxed Processor Cooling Requirements ...............................................82
6.3 Electrical Requirements for the Boxed Intel® Pentium® III Processor.................83
6.3.1 Fan Heatsink Power Supply...................................................................83
7.0 Processor Signal Description.............................................................................85
7.1 Alphabetical Signals Reference ..........................................................................85
7.2 Signal Summaries ...............................................................................................92
Datasheet 5
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figures
1 Second Level (L2) Cache Implementation ...........................................................8
2 AGTL+/AGTL Bus Topology in a Uniprocessor Configuration ............................14
3 AGTL+/AGTL Bus Topology in a Dual-Processor Configuration ........................14
4 Stop Clock State Machine...................................................................................15
5 Processor VccCMOS Package Routing ................................................................18
6 Differential Clocking Example .............................................................................20
7 BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........25
8 Slew Rate (23A Load Step).................................................................................33
9 Generic Clock Waveform ....................................................................................41
10 BCLK, PICCLK, and TCK Generic Clock Waveform...........................................42
11 System Bus Valid Delay Timings ........................................................................42
12 System Bus Setup and Hold Timings..................................................................43
13 System Bus Reset and Configuration Timings....................................................43
14 Platform Power-On Sequence Timings ...............................................................44
15 Power-On Reset and Configuration Timings.......................................................45
16 BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................47
17 Low to High AGTL+ Receiver Ringback Tolerance.............................................48
18 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform.......................53
19 Maximum Acceptable AGTL Overshoot/Undershoot Waveform.........................53
20 Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and
Ringback 1 ..........................................................................................................54
21 Processor Functional Die Layout for FC-PGA.....................................................58
22 FC-PGA and FC-PGA2 Package Types .............................................................60
23 Package Dimensions...........................................................................................61
24 Package Dimensions for FC-PGA2.....................................................................63
25 FC-PGA2 Flatness Specification.........................................................................64
26 Top Side Processor Markings for FC-PGA (up to CPUID 0x686H) ....................65
27 Top Side Processor Markings for FC-PGA (for CPUID 0x68AH)).......................65
28 Top Side Processor Markings for FC-PGA2 .......................................................66
29 Volumetric Keep-Out for FC-PGA and FC-PGA2................................................66
30 Component Keep-Out .........................................................................................67
31 Intel® Pentium® III Processor Pinout ...................................................................68
32 Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket ..........80
33 Dimensions of Mechanical Step Feature in Heatsink Base.................................81
34 Dimensions of Notches in Heatsink Base ...........................................................82
35 Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor Fan
Heatsinks in the PGA370 Socket ........................................................................83
36 Boxed Processor Fan Heatsink Power Cable Connector Description.................84
37 Motherboard Power Header Placement Relative to the Boxed
Intel® Pentium® III Processor ..............................................................................84
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
6 Datasheet
Tables
1 Processor Identification.......................................................................................10
2 Voltage Identification Definition...........................................................................21
3 System Bus Signal Groups 1 ..............................................................................23
4 System Bus Signal Groups (AGTL)1 ..................................................................23
5 Frequency Select Truth Table for BSEL[1:0] ......................................................26
6 Absolute Maximum Ratings ................................................................................26
7 Voltage and Current Specifications ....................................................................28
8 PL Slew Rate Data (23A) ....................................................................................33
9 AGTL / AGTL+ Signal Groups DC Specifications ..............................................34
10 Non-AGTL+ Signal Group DC Specifications .....................................................34
11 Non-AGTL Signal Group DC Specifications .......................................................35
12 Processor AGTL+ Bus Specifications ................................................................36
13 Processor AGTL Bus Specifications ..................................................................36
14 System Bus AC Specifications (SET Clock) .......................................................37
15 System Bus Timing Specifications (Differential Clock) .......................................38
16 System Bus AC Specifications (AGTL+ or AGTL Signal Group) ........................39
17 System Bus AC Specifications (CMOS Signal Group) .......................................40
18 System Bus AC Specifications (Reset Conditions) ............................................40
19 System Bus AC Specifications (APIC Clock and APIC I/O) ................................40
20 Platform Power-On Timings ................................................................................40
21 BCLK/PICCLK Signal Quality Specifications for Simulation at the
Processor Pins ...................................................................................................46
22 BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
in a Differential Clock Platform for AGTL ............................................................46
23 AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins ....................................................................................................................47
24 Example Platform Information.............................................................................50
25 100 MHz AGTL+ / AGTL Signal Group Overshoot/Undershoot Tolerance at
Processor Pins ....................................................................................................51
26 133 MHz AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance ..........52
27 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at
Processor Pins ....................................................................................................52
28 Signal Ringback Specifications for Non-AGTL+ Signal Simulations at the
Processor Pins ....................................................................................................55
29 Signal Ringback Specifications for Non-AGTL Signal Simulations at
the Processor Pins .............................................................................................55
30 Intel® Pentium® III Processor Thermal Design Power for the FC-PGA Package ..
56
31 Intel® Pentium® III Processor for the FC-PGA2 Package Thermal
Design Power......................................................................................................57
32 Processor Functional Die Layout for FC-PGA ....................................................58
33 Thermal Diode Parameters .................................................................................59
34 Thermal Diode Interface......................................................................................59
35 Intel® Pentium® III Processor Package Dimensions..........................................61
36 Processor Die Loading Parameters for FC-PGA ................................................62
37 Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package .....63
38 Processor Case Loading Parameters for FC-PGA2 ...........................................64
39 Signal Listing in Order by Signal Name ..............................................................69
40 Signal Listing in Order by Pin Number ................................................................74
Datasheet 7
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
41 Fan Heatsink Power and Signal Specifications...................................................84
42 Signal Description ...............................................................................................85
43 Output Signals.....................................................................................................92
44 Input Signals........................................................................................................92
45 Input/Output Signals (Single Driver)....................................................................94
46 Input/Output Signals (Multiple Driver) .................................................................94
8 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
1.0 Introduction
The Intel® Pentium® III processor for the PGA370 socket is the next member of the P6 family, in
the Intel IA-32 processor line and hereafter will be referred to as the “Pentium III processor”, or
simply “the processor”. The processor uses the same core and offers the same performance as the
Pentium III processor for the SC242 connector, but utilizes a package technology called flip-chip
pin grid array, or FC-PGA. This package utilizes the same 370-pin zero insertion force socket
(PGA370) used by the Intel® CeleronTM processor. Thermal solutions are attached directly to the
back of the processor core package without the use of a thermal plate or heat spreader. As core
frequencies increase, the need for better power dissipation arises, so an Integrated Heat Spreader
(IHS) has been introduced at the higher frequencies near 1B GHz. The package with an IHS is
called FC-PGA2.
The Pentium III processor, like its predecessors in the P6 family of processors, implements a
Dynamic Execution microarchitecture—a unique combination of multiple branch prediction, data
flow analysis, and speculative execution. This enables these processors to deliver higher
performance than the Pentium processor, while maintaining binary compatibility with all previous
Intel Architecture processors. The processor also executes Intel® MMXTM technology instructions
for enhanced media and communication performance just as it’s predecessor, the Pentium III
processor. Additionally, Pentium III processor executes Streaming SIMD (single-instruction,
multiple data) Extensions for enhanced floating point and 3-D application performance. The
concept of processor identification, via CPUID, is extended in the processor family with the
addition of a processor serial number. Refer to the Intel® Processor Serial Number application note
for more detailed information. The processor utilizes multiple low-power states such as
AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times.
The processor includes an integrated on-die, 256-KB, 8-way set associative level-two (L2) cache.
The L2 cache implements the new Advanced Transfer Cache Architecture with a 256-bit wide bus.
The processor also includes a 16-KB level one (L1) instruction cache and 16-KB L1 data cache.
These cache arrays run at the full speed of the processor core. As with the Pentium III processor for
the SC242 connector, the Pentium III processor for the PGA370 socket has a dedicated L2 cache
bus, thus maintaining the dual independent bus architecture to deliver high bus bandwidth and
performance (see Figure 1). Memory is cacheable for 64 GB of addressable memory space,
allowing significant headroom for desktop systems. Refer to the Specification Update document
for this processor to determine the cacheability and cache configuration options for a specific
processor. The Specification Update document can be requested at your nearest Intel sales office.
The processor utilizes the same multiprocessing system bus technology as the Pentium II processor.
This allows for a higher level of performance for both uni-processor and two-way multiprocessor
systems. The system bus uses a variant of GTL+ signaling technology called Assisted Gunning
Transceiver Logic (AGTL+/AGTL) signaling technology.
Figure 1. Second Level (L2) Cache Implementation
Processor
Core Tag L2 Processor
Core
L2
Intel® Pentium® III SECC2 Processor Intel® Pentium® III FC-PGA Processor
Datasheet 9
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
1.1 Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
chipset components), and other bus agents.
1.1.1 Package and Processor Terminology
The following terms are used often in this document and are explained here for clarification:
• Pentium III processor - The entire product including all internal components.
• PGA370 socket - 370-pin Zero Insertion Force (ZIF) socket which a FC-PGA or PPGA
packaged processor plugs into.
• FC-PGA - Flip Chip Pin Grid Array. The package technology used on Pentium III processors
for the PGA370 socket.
• FC-PGA2 - Flip Chip Pin Grid Array with an Integrated Heat Spreader (IHS). The package
technology used on Pentium III processors for the PGA370 socket for increased power
dissipation away from the die. The IHS covers the die and has a very low thermal resistance.
• Integrated Heat Spreader (IHS) - The IHS is a metal cover on the die and is an integral part
of the CPU. The IHS promotes heat spreading away from the die backside to ease thermal
constraints.
• Advanced Transfer Cache (ATC) - New L2 cache architecture unique to the 0.18 micron
Pentium III processors. ATC consists of microarchitectural improvements that provide a higher
data bandwidth interface into the processor core that is completely scaleable with the
processor core frequency.
• Keep-out zone - The area on or near a FC-PGA packaged processor that system designs can
not utilize.
• Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.
• OLGA - Organic Land Grid Array. The package technology for the core used in S.E.C.C. 2
processors that permits attachment of the heatsink directly to the die.
• PPGA - Plastic Pin Grid Array. The package technology used for Celeron processors that
utilize the PGA370 socket.
• Processor - For this document, the term processor is the generic form of the Pentium III
processor for the PGA370 socket in the FC-PGA package.
• Processor core - The processor’s execution engine.
• S.E.C.C. - The processor package technology called “Single Edge Contact Cartridge”. Used
with Intel® Pentium® II processors.
• S.E.C.C. 2 - The follow-on to S.E.C.C. processor package technology. This differs from its
predecessor in that it has no extended thermal plate, thus reducing thermal resistance. Used
with Pentium III processors and latest versions of the Pentium II processor.
10 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
• SC242 - The 242-contact slot connector (previously referred to as slot 1 connector) that the
S.E.C.C. and S.E.C.C. 2 plug into, just as the Intel® Pentium® Pro processor uses socket 8.
The cache and L2 cache are an industry designated names.
1.1.2 Processor Naming Convention
A letter(s) is added to certain processors (e.g., 600EB MHz) when the core frequency alone may
not uniquely identify the processor. Below is a summary of what each letter means as well as a
table listing all the available Pentium III processors for the PGA370 socket.
“B” — 133 MHz System Bus Frequency
“E” — Processor with “Advanced Transfer Cache” (CPUID 068xh and greater)
NOTES:
1. Refer to the Pentium® III Processor Specification Update for the exact CPUID for each processor.
2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.
With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same
frequency as the processor core and has enhanced buffering.
Table 1. Processor Identification
Processor Core Frequency
(MHz)
System Bus
Frequency
(MHz)
L2 Cache Size
(Kbytes)
L2 Cache
Type2 CPUID1
500E 500 100 256 ATC 068xh
533EB 533 133 256 ATC 068xh
550E 550 100 256 ATC 068xh
600E 600 100 256 ATC 068xh
600EB 600 133 256 ATC 068xh
650 650 100 256 ATC 068xh
667 667 133 256 ATC 068xh
700 700 100 256 ATC 068xh
733 733 133 256 ATC 068xh
750 750 100 256 ATC 068xh
800 800 100 256 ATC 068xh
800EB 800 133 256 ATC 068xh
850 850 100 256 ATC 068xh
866 866 133 256 ATC 068xh
900 900 100 256 ATC 068xh
933 933 133 256 ATC 068xh
1 GHz 1000 100 256 ATC 068xh
1B GHz 1000 133 256 ATC 068xh
1.10 GHz 1100 100 256 ATC 068xh
1.13 GHz 1133 133 256 ATC 068xh
Datasheet 11
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
1.2 Related Documents
The reader of this specification should also be familiar with material and concepts presented in the
following documents 1,2:
Document Intel Document Number
AP-485, Intel® Processor Identification and the CPUID Instruction 241618
AP-585, Pentium® II Processor GTL+ Guidelines 243330
AP-589, Design for EMI 243334
AP-905, Pentium® III Processor Thermal Design Guidelines 245087
AP-907, Pentium® III Processor Power Distribution Guidelines 245085
AP-909, Intel® Processor Serial Number 245125
Intel® Architecture Software Developer's Manual 243193
Volume I: Basic Architecture 243190
Volume II: Instruction Set Reference 243191
Volume III: System Programming Guide 243192
P6 Family of Processors Hardware Developer’s Manual 244001
Pentium® II Processor Developer’s Manual 243502
Pentium® III Processor Datasheet for SECC2 244452
Pentium® III Processor Datasheet for PGA370 245264
Pentium® III Processor Specification Update 244453
Intel® CeleronTM Processor Datasheet 243658
Intel® CeleronTM Processor Specification Update 243748
370-Pin Socket (PGA370) Design Guidelines 244410
PGA370 Heat Sink Cooling in MicroATX Chassis 245025
Intel® 810E Chipset Platform Design Guide 290675
Intel® 815 B-step Chipset Platform Design Guide3
Intel® 815E Chipset Platform Design Guide 298234
Intel® 820 Chipset Platform Design Guide 290631
Intel® 840 Chipset Platform Design Guide 298021
CK98 Clock Synthesizer/Driver Design Guidelines 245338
Intel® 810E Chipset Clock Synthesizer/Driver Specification 3
VRM 8.4 DC-DC Converter Design Guidelines 245335
Pentium III Processor for the PGA370 Socket I/O Buffer Models, XTK/XNS*
Format 3
Pentium® Pro Processor BIOS Writer’s Guide 3
Extensions to the Pentium® Pro Processor BIOS Writer’s Guide rev. 3.7 3
Pentium® III Thermal/Mechanical Solution Functional Guidelines 245241
Intel®Pentium® III Processor in the FC-PGA2 Package Thermal Design Guide 249660
12 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, this reference material can be found on the Intel Developer’s Website located at
http://developer.intel.com.
2. For a complete listing of Pentium III processor reference material, please refer to the Intel Developer’s
Website at http://developer.intel.com/design/PentiumIII/.
3. This material is available through an Intel field sales representative.
Datasheet 13
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.0 Electrical Specifications
2.1 Processor System Bus and VREF
The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Pentium Pro processor system bus specification is similar to the GTL specification, but was
enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Intel® Pentium® II
Processor Developer’s Manual.
Current P6 family processors vary from the Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Celeron, Pentium II, and
Pentium III processors are actively driven to VTT for one clock cycle after the low to high transition
to improve rise times. These signals should still be considered open-drain and require termination
to a supply that provides the high signal level. Because this specification is different from the
standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and other
documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both be
used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
Note that some Pentium III processors with CPUID 068xh support the AGTL specification in
addition to the AGTL+ specification. AGTL logic and AGTL+ logic are not compatible with each
other due to differences with the signal switching levels. Processors that do not support the AGTL
specification cannot be installed into platforms where the chipset only supports the AGTL signal
levels. For more information on AGTL or AGTL+ routing, please refer to the appropriate platform
design guide.
Both AGTL and AGTL+ inputs use differential receivers which require a reference signal (VREF).
VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by
the motherboard to the PGA370 socket for the processor core. Local VREF copies should also be
generated on the motherboard for all other devices on the AGTL+ (AGTL) system bus. Termination
(usually a resistor at each end of the signal trace) is used to pull the bus up to the high voltage level
and to control reflections on the transmission line. The processor contains on-die termination
resistors that provide termination for one end of the bus, except for RESET#. These specifications
assume another resistor at the end of each signal trace to ensure adequate signal quality for the
AGTL+ (AGTL) signals and provide backwards compatibility for the Celeron processor; see Table
12 for the bus termination voltage specifications for AGTL+. Refer to the Intel® Pentium® II
Processor Developer’s Manual for the AGTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design and eliminate backwards
compatibility for Celeron processors in the PPGA package. Single-ended termination designs must
still provide an AGTL+ (AGTL) termination resistor on the motherboard for the RESET# signal.
Figure 2 is a schematic representation of the AGTL+ (AGTL) bus topology for the Pentium III
processors in the PGA370 socket. Figure 3 is a schematic representation of the AGTL+/AGTL bus
topology in a dual-processor configuration with Pentium III processors in the PGA370 socket.
Both AGTL+ and AGTL bus depend on incident wave switching. Therefore, timing calculations for
AGTL+ or AGTL signals are based on flight time as opposed to capacitive deratings. Analog signal
simulation of the system bus including trace lengths is highly recommended when designing a
14 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination
resistors (i.e., those on the processor die). Such designs will not match the solution space allowed
for by installation of termination resistors on the baseboard.
2.2 Clock Control and Low Power States
Processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 4 for a visual representation of the processor low-power states.
Figure 2. AGTL+/AGTL Bus Topology in a Uniprocessor Configuration
Figure 3. AGTL+/AGTL Bus Topology in a Dual-Processor Configuration
Processor Chipset
Processor Chipset Processor
Datasheet 15
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide located on the developer.intel.com website.
2.2.1 Normal State—State 1
This is the normal operating state for the processor.
2.2.2 AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI,
INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT
state.
Figure 4. Stop Clock State Machine
PCB757a
2. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allowed.
HALT Instruction and
HALT Bus Cycle Generated
INIT#, BINIT#, INTR,
SMI#, RESET#
1. Normal State
Normal execution.
STPCLK#
Asserted
STPCLK#
De-asserted
3. Stop Grant State
BCLK running.
Snoops and interrupts allowed.
SLP#
Asserted
SLP#
De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK
Input
Stopped
BCLK
Input
Restarted
6. Deep Sleep State
BCLK stopped.
No snoops or interrupts allowed.
4. HALT/Grant Snoop State
BCLK running.
Service snoops to caches.
Snoop Event Occurs
Snoop Event Serviced
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK# Asserted
STPCLK# De-asserted
and Stop-Grant State
entered from
AutoHALT
, NMI
16 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor returns execution to the HALT
state.
2.2.3 Stop-Grant State—State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# and FLUSH# are not serviced during the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant
state. A transition back to the Normal state occurs with the deassertion of the STPCLK# signal.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the
system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) occurs with the
assertion of the SLP# signal.
While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] are latched by the processor, and only
serviced when the processor returns to the Normal state. Only one occurrence of each event is
recognized and serviced upon return to the Normal state.
2.2.4 HALT/Grant Snoop State—State 4
The processor responds to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor stays in this state until the snoop on the system bus has been serviced
(whether by the processor or another agent on the system bus). After the snoop is serviced, the
processor returns to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5 Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.
Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
Datasheet 17
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6 Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK1 input (after the Sleep state was entered
from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK
is stopped. It is recommended that the BCLK1 input be held low during the Deep Sleep State.
Stopping of the BCLK1 input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7 Clock Control
BCLK2 provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.2
2.3 Power and Ground Pins
The operating voltage of the Pentium III processor for the PGA370 socket is the same for the core
and the L2 cache; VCCCORE. There are four pins defined on the package for voltage identification
(VID). These pins specify the voltage required by the processor core. These have been added to
cleanly support voltage specification variations on current and future processors.
For clean on-chip power and voltage reference distribution, the Pentium III processors in the
PGA370 socket have 75 VCCCORE, 8 VREF (7 for AGTL platforms), 15 VTT, and 77 VSS (ground)
inputs. VCCCORE inputs supply the processor core, including the on-die L2 cache. VTT inputs
1. For processors using AGTL level bus with differential clocking, the deep sleep state is entered by stopping BCLK and BCLK# input.
2. For processors using AGTL level bus with differential clocking this would also include the BCLK# signal as well.
18 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
(1.5 V/1.25 V) are used to provide an AGTL+/AGTL termination voltage to the processor, and the
VREF inputs are used as the AGTL+/AGTL reference voltage for the processor. Note that not all
VTT inputs must be connected to the VTT supply. Refer to Section 5.4 for more details.
On the motherboard, all VCCCORE pins must be connected to a voltage island (an island is a portion
of a power plane that has been divided, or an entire plane). In addition, the motherboard must
implement the VTT pins as a voltage island or large trace. Similarly, all GND pins must be
connected to a system ground plane.
Three additional power related pins exist on a processors utilizing the PGA370 socket. They are
VCC1.5, VCC2.5 and VCCCMOS.
The VCCCMOS pin provides the CMOS voltage for the pull-up resistors required on the system
platform. A 2.5 V source must be provided to the VCC2.5 pin and a 1.5 V source must be provided
to the VCC1.5 pin. The source for VCC1.5 must be the same as the one supplying VTT. The processor
routes the compatible CMOS voltage source (1.5 V or 2.5 V) through the package and out to the
VCCCMOS output pin. Processors based on 0.25 micron technology (e.g., the Celeron processor)
utilize 2.5 V CMOS buffers. Processors based on 0.18 micron technology (e.g., the Pentium III
processor for the PGA370 socket) utilize 1.5 V CMOS buffers. The signal VCOREDET can be used
by hardware on the motherboard to detect which CMOS voltage the processor requires. A
VCOREDET connected to VSS within the processor indicates a 1.5 V requirement on VCCCMOS.
Refer to Figure 5.
Each power signal must meet the specifications stated in Table 7 on page 28.
2.3.1 Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter specifications.
Figure 5. Processor VCCCMOS Package Routing
Intel®
Pentium® III
Processor 0.1 uF
2.5V Supply
2.5V
1.5V Supply
1.5V
VCCCMOS
*ICH or
Other Logic
CMOS
Pullups
CMOS Signals
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel® Pentium® III processor
for the PGA370 socket.
Datasheet 19
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.4 Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 7. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1 Processor VCCCORE and AGTL+ (AGTL) Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 7) while maintaining the required tolerances (also defined in Table 7). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ (AGTL) bus operation. See the AGTL+ buffer specification in the
Intel® Pentium® II Processor Developer's Manual for more information. Also, refer to the
appropriate platform design guide for recommended capacitor component placement. The
minimum recommendation for the processor decoupling is listed below. All capacitors should be
placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The
capacitors are arranged to minimize the overall inductance between the VCCCORE and Vss power
pins.
1. VCCCORE decoupling - 4.7 µF capacitors in a 1206 package.
2. VTT decoupling - 0.1 µF capacitors in 0603 package.
3. VREF decoupling - 0.1 µF and 0.001 µF capacitors in 0603 package placed near the VREF pins.
For additional decoupling requirements, please refer to the appropriate platform design guide for
recommended capacitor component value, quantity and placement.
2.5 Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+/
AGTL system bus timing parameters are specified with respect to the rising edge of the BCLK
input.
The Coppermine-T processor will implement an auto-detect mechanism that will let the processor
use either single-ended or differential signaling for the system bus and processor clocking. The
processor checks to see if the signal on pin Y33 is toggling. If this signal is toggling then the
processor operates in differential mode. Refer to Figure 6 for a differential clocking example.
Resistor values and clock topology are listed in the appropriate platform design guide for a
differential implementation.
20 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Note: References to BCLK throughout this document will also imply to its complement signal, BCLK#,
in differential implementations and when noted otherwise.
For a differential clock input, all AGTL system bus timing parameters are specified with respect to
the crossing point of the rising edge of the BCLK input and the falling edge of the BCLK# input.
See the P6 Family of Processors Hardware Developer's Manual for further details.
Note: For differential clocking, the reference voltage of the BCLK in the P6 Family of Processors
Hardware Developer's Manual is re-defined as the crossing point of the BCLK and the BCLK#
inputs.
2.5.1 Mixing Processors of Different Frequencies
In two-way MP (multi-processor) systems, mixing processors of different internal clock
frequencies is not supported and has not been validated. Pentium III processors do not support a
variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not
valid. However, mixing processors of the same frequency but of different steppings is supported.
Details on support for mixed steppings is provided in the Pentium® III Processor Specification
Update.
Note: Not all Pentium III processors for the PGA370 socket are validated for use in dual processor (DP)
systems. Refer to the Pentium® III Processor Specification Update to determine which processors
are DP capable.
2.6 Voltage Identification
There are four voltage identification pins on the PGA370 socket. These pins can be used to support
automatic selection of VCCCORE voltages. These pins are not signals, but are either an open circuit
or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage
required by the processor core. The VID pins are needed to cleanly support voltage specification
variations on current and future processors. VID[3:0] are defined in Table 2. A ‘1’ in this table
refers to an open pin and a ‘0’ refers to a short to ground. The voltage regulator or VRM must
supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future processors, the range of values in bold in Table 2
should be supported. A smaller range will risk the ability of the system to migrate to a higher
performance processor and/or maintain compatibility with current processors.
Figure 6. Differential Clocking Example
BCLK
BCLK#
Clock
Driver
Processor or
Chipset
Datasheet 21
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on baseboard.
3. To ensure a system is ready for the Pentium III and Celeron processors, the values in BOLD in Table 2 should
be supported.
Note that the ‘1111’ (all opens) ID can be used to detect the absence of a processor core in a given
socket as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see Section 7.0).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[3:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-
DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10 kΩmay be used to connect theVIDsignals to the
converter input. Note that no changes have been made to the physical connector or pin definitions
between the Intel-enabled VRM 8.2 and VRM 8.4 specifications.
Note: VRM 8.5 specification uses five VID pin assignments VID[3:0, 25mV] and it is not compatible
with VRM 8.4. Some Pentium III processors with CPUID 068xh are capable of supporting both
VRM 8.4 and VRM 8.5 specifications. Please refer to the Pentium III Specification Update for a
listing of processors that support both VRM specifications.
Table 2. Voltage Identification Definition 1, 2
VID3 VID2 VID1 VID0 VccCORE
1 1 1 1 1.30
1 1 1 0 1.35
1 1 0 1 1.40
1 1 0 0 1.45
1 0 1 1 1.50
1 0 1 0 1.55
1 0 0 1 1.603
1 0 0 0 1.653
0 1 1 1 1.703
0 1 1 0 1.753
0 1 0 1 1.80 3
0 1 0 0 1.85 3
0 0 1 1 1.90 3
0 0 1 0 1.95 3
0 0 0 1 2.00 3
0 0 0 0 2.05 3
1 1 1 1 No Core
22 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.7 Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to VCCCORE, VREF, VSS, VTT, or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Section 5.4 for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
VCCCMOS even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (VIH) and logic low (VIL) requirements are met. See Table 10 and Table 11
for DC specifications of non-AGTL+/AGTL signals.
Unused AGTL+ (or AGTL) inputs must be properly terminated to VTT on PGA370 socket
motherboards which support the Celeron and the Pentium III processors. For designs that intend to
only support the PentiumIII processor, unused AGTL+ inputs will be terminated by the processor’s
on-die termination resistors and thus do not need to be terminated on the motherboard. However,
RESET# must always be terminated on the motherboard as the Pentium III processor for the
PGA370 socket does not provide on-die termination of this input.
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
VCCCMOS and meet VIH requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8 Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Pentium III processor for the
PGA370 socket includes on-die termination. Motherboard designs that also support Celeron
processors in the PPGA package will need to provide AGTL+ termination on the system
motherboard as well. Platform designs that support dual processor configurations will need
to provide AGTL+ termination, via a termination package, in any socket not populated with
a processor. Please refer to the Pentium III Processor Specification Update for a complete
listing of the processors that support the AGTL and AGTL+ specifications. Note that AGTL
platforms do not support the Celeron processor in the PPGA package.
Both AGTL+ and AGTL input signals have differential input buffers which use VREF as a reference
signal. AGTL+ output signals require termination to 1.5 V while AGTL output signals require
termination to 1.25 V. In this document, the term “AGTL+ Input” refers to the AGTL+ input group
as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) are only 1.5 V tolerant and must be pulled up to VCCCMOS. The CMOS, APIC, and
TAP outputs are open drain and must be pulled high to VCCCMOS. This ensures correct operation
for current Pentium III and Celeron processors.
Datasheet 23
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The groups and the signals contained within each group are shown in Table 3 and Table 4. Refer to
Section 7.0 for a description of these signals.
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for VccCMOS (1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V tolerant.
5. VCCCORE is the power supply for the processor core and is described in Section 2.6.
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the motherboard.
VSS is system ground.
VCC1.5, VCC2.5, VccCMOS are described in Section 2.3.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium® III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pull-down resistor value.
Table 3. System Bus Signal Groups 1
Group Name Signals
AGTL+ Input BPRI#, BR1#7, DEFER#, RESET# 6,RESET2#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output PRDY#
AGTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input3 A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input4 PWRGOOD
CMOS Output3 FERR#, IERR#, THERMTRIP#
System Bus
Clock4 BCLK
APIC Clock4 PICCLK
APIC I/O3 PICD[1:0]
Power/Other5
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS,
VCCCORE, VREF, VSS, VTT, Reserved
Table 4. System Bus Signal Groups (AGTL)1 (Sheet 1 of 2)
Group Name Signals
AGTL Input9 BPRI#, BR1#7, DEFER#, RESET#6, RSP#, TRDY#, RS[2:0]#
AGTL Output9 PRDY#
AGTL I/O9 A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,
CMOS Input3 A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input
(1.8 V) PWRGOOD
CMOS Output FERR#3, IERR#3, THERMTRIP#3, VID[3:0]13, BSEL[1:0]13
24 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for VccCMOS (1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V tolerant.
5. VCCCORE is the power supply for the processor core and is described in Section 2.6.
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the motherboard.
VSS is system ground.
VCC1.5, VCC2.5, VccCMOS are described in Section 2.3.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium® III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pull-down resistor value.
9. These signals are also classified as AGTL. Refer to the Pentium® III Processor Specification Update for a
complete listing of processors that support the AGTL and AGTL+ specifications.
10.For differential clock systems, the CLKREF pin becomes BCLK#.
11.For the Coppermine-T differential clock, this signal has been redefined to 2.0 V tolerant.
12. 1.25 V signal for Differential clock application and 2.5 V for Single-ended clock application.
13. This signal is 3.3 V.
2.8.1 Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK.
System Bus
Clock10, 12
(1.25 V/2.5 V)
BCLK, BCLK0#
APIC Clock
(2.0 V) PICCLK11
APIC I/O3 PICD[1:0]
Power/Other5
BSEL[1:0], CLKREF10, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS,
VCCCORE, VREF, VSS, VTT, Reserved
Table 4. System Bus Signal Groups (AGTL)1 (Sheet 2 of 2)
Group Name Signals
Datasheet 25
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.8.2 System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency for the processor. The BSEL signals are
also used by the chipset and system bus clock generator. Table 5 defines the possible combinations
of the signals and the frequency associated with each combination. The frequency selection is
determined by the processor(s) and driven out to the chipset and clock generator. All system bus
agents must operate at the same frequency determined by the processor. The Pentium III
processor for the PGA370 socket operates at 100 MHz or 133 MHz system bus frequency;
66 MHz system bus operation is not supported. Individual processors will only operate at their
specified front side bus (FSB) frequency, either 100 MHz or 133 MHz, not both. Over or underclocking
the system bus frequency outside the specified rating marked on the package is not
recommended.
On motherboards that support operation at either 100 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in Figure 7. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implementation details.
Figure 7. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
Processor
BSEL0 BSEL1
Chipset
Clock Driver
1 KΩ 1 KΩ
3.3V 3.3V
10 KΩ
Note 1
10 KΩ
Note 2
10 KΩ
Note 2
26 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.9 Maximum Ratings
Table 6 contains processor stress ratings only. Functional operation at the absolute maximum and
minimum is not implied nor guaranteed. The processor should not receive a clock while subjected
to these conditions. Functional operating conditions are given in the AC and DC tables in
Section 2.10 through Section 2.12. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist damage from
static electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
NOTES:
1. Input voltage can never exceed VSS + 2.18 V.
2. Input voltage can never go below VTT - 2.18 V.
3. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD) and APIC bus signal groups only.
4. Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD only.
Table 5. Frequency Select Truth Table for BSEL[1:0]
BSEL1 BSEL0 Frequency
0 0 66 MHz (unsupported)
0 1 100 MHz
1 0 Reserved
1 1 133 MHz
Table 6. Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
TSTORAGE Processor storage temperature –40 85 °C
VccCORE and
VTT
Processor core voltage and termination
supply voltage with respect to VSS
–0.5 2.1 V
VinAGTL AGTL+ buffer input voltage VTT - 2.18 2.18 V 1, 2
VinCMOS1.5
CMOS buffer DC input voltage with respect
to VSS
VTT - 2.18 2.18 V 1, 2, 3
VinCMOS2.5
CMOS buffer DC input voltage with respect
to VSS
-0.58 3.18 V 4
IVID Max VID pin current -0.3 5 mA
ICPUPRES# Max CPUPRES# pin current 5 mA
Datasheet 27
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.10 Processor DC Specifications
The processor DC specifications in this section are defined at the PGA370 socket pins (bottom side
of the motherboard). See Section 7.0 for the processor signal descriptions and Section 5.4 for the
signal listings.
Most of the signals on the processor system bus are in the AGTL+ (AGTL) signal group. These
signals are specified to be terminated to 1.5 V for AGTL+ or 1.25 V for AGTL. The DC
specifications for these signals are listed in Table 9 on page 34.
To allow connection with other devices, the clock, CMOS, and APIC signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 11 on
page 35.
Table 7 through Table 12 list the DC specifications for the Pentium III processor for the PGA370
socket. Specifications are valid only while meeting specifications for junction temperature, clock
frequency, and input voltages. Care should be taken to read all notes associated with each
parameter.
28 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Table 7. Voltage and Current Specifications 1, 2 (Sheet 1 of 5)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
VCCCORE VCC for Processor Core
500E
MHz
0x681 1.60
V
3,4
0x683 1.60 3,4
0x686 n/a 3,4
533EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 n/a 3,4
550E
MHz
0x681 1.60 3,4
0x683 1.65 3,4
0x686 1.70 3,4
600E
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
600EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
650
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
667
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
700
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
733
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
750
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
Datasheet 29
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
VCCCORE VCC for Processor Core
800
MHz
0x681 1.65
V
3,4
0x683 1.65 3,4
0x686 1.70 3,4
800EB
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
850
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
866
MHz
0x681 1.65 3,4
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4
900
MHz
0x686 1.70 3,4
0x68A 1.75 3,4
933
MHz
0x683 1.65 3,4
0x686 1.70 3,4
0x68A 1.75 3,4,20
1 GHz 0x68A 1.75 3,4
1B
GHz
0x686 1.70 3,4
0x686 1.76 3,4,18,19
0x68A 1.75 3,4,20
1.10
GHz 0x68A 1.75 3,4
1.13
GHz 0x68A 1.75 3,4
Table 7. Voltage and Current Specifications 1, 2 (Sheet 2 of 5)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
30 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
VTT
Static AGTL+ bus
termination voltage
Static AGTL bus
termination voltage
1.455
1.213
1.50
1.25
1.545
1.288
V
V
1.5 ±3% 5,16
1.25 ±3% 5,16,17
VTT
Transient AGTL+ bus
termination voltage
Transient AGTL bus
termination voltage
1.365
1.138
1.50
1.25
1.635
1.363
V
V
1.5 ±9% 5
1.25 ±9% 5,17
Vcc1.5
Static AGTL+ bus
termination voltage 1.455 1.50 1.545 V 1.5 ±3%
VREF
AGTL+ input reference
voltage -2% 2/3
VTT
+2% V ±2%, 7
VCLKREF
CLKREF input
reference voltage 1.169 1.25 1.331 V ±6.5%, 15
Baseboard
VCCCORE
Tolerance,
Static
Processor core voltage
static tolerance level at
the PGA370 socket
pins
–0.080
0.001
0.040
0.100
V
6
18, 19
Baseboard
VCCCORE
Tolerance,
Transient
Processor core voltage
transient tolerance level
at the PGA370 socket
pins
–0.130
–0.110
–0.025
0.080
0.080
0.130
V
6
17
18, 19
Table 7. Voltage and Current Specifications 1, 2 (Sheet 3 of 5)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
Datasheet 31
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
ICCCORE ICC for processor core
500E
MHz 0x683 10.0
A
3, 8, 9
600E
MHz
0x686 12.0 3, 8, 9
0x68A 12.6 3, 8, 9
600EB
MHz 0x686 12.0 3, 8, 9
650
MHz 0x686 13.0 3, 8, 9
667B
MHz 0x686 13.3 3, 8, 9
700
MHz
0x686 14.0 3, 8, 9
0x68A 14.8 3, 8, 9
733B
MHz
0x686 14.6 3, 8, 9
0x68A 15.4 3, 8, 9
750
MHz
0x686 15.0 3, 8, 9
0x68A 15.7 3, 8, 9
800
MHz 0x686 16.0 3, 8, 9
800EB
MHz
0x686 16.0 3, 8, 9
0x68A 16.6 3, 8, 9
850
MHz
0x686 16.2 3, 8, 9
0x68A 17.3 3, 8, 9
866
MHz
0x686 16.3 3, 8, 9
0x68A 17.6 3, 8, 9
900
MHz
0x686 17.0 3, 8, 9
0x68A 18.4 3, 8, 9
933
MHz
0x686 17.7 3, 8, 9
0x68A 18.8 3, 8, 9,20
1 B
GHz
0x686 19.4 3, 8, 9
0x68A 20.2 3, 8, 9, 20
1 GHz 0x68A 20.2 3, 8, 9
1.10
GHz 0x68A 22.6 3, 8, 9
1.13
GHz 0x68A 22.6 3, 8, 9,20
Table 7. Voltage and Current Specifications 1, 2 (Sheet 4 of 5)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
32 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
Celeron processor, see the Intel® CeleronTM Processor Datasheet.
3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. VTT and Vcc1.5 must be held to 1.5 V ±9% while the AGTL+ bus is active. It is required that VTT and Vcc1.5 be
held to 1.5 V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the soldered-side of the motherboard. VCCCORE must return to within the static
voltage specification within 100 µs after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelines for further details.
7. VREF should be generated from VTT by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
Intel® Pentium® II Processor Developer’s Manual for more details on VREF.
8. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VccCORE
(VccCORE_TYP). In this case, the maximum current level for the regulator, IccCORE_REG, can be reduced from
the specified maximum current IccCORE _MAX and is calculated by the equation:
IccCORE_REG = IccCORE_MAX × (VccCORE_TYP - VccCORE_STATIC_TOLERANCE) / VccCORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see Section 2.1).
11.The current specified is also for AutoHALT state.
12.Maximum values are specified by design/characterization at nominal VccCORE.
13.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25 V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5 V or 3.3 V supply. VTT should not be used due to risk of AGTL+ switching noise coupling to this analog
reference.
16.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables above.
17.This specification applies to PGA370 processors operating at frequencies of 933 MHz or higher.
ICCCMOS ICC for VccCMOS 250 mA
ICLKREF
CLKREF voltage
supply current 60 µA
IVTT
Termination voltage
supply current 2.7 A 10
ISGnt
ICC Stop-Grant for
processor core 6.9 A 8, 11
ISLP
ICC Sleep for processor
core 6.9 A 8
IDSLP
ICC Deep Sleep for
processor core 6.6 A 8
dICCCORE/dt Power supply current
slew rate 240 A/µs 12, 13, 14
dIvTT/dt Termination current
slew rate 8 A/µs 12, 13, See
Table 12
Table 7. Voltage and Current Specifications 1, 2 (Sheet 5 of 5)
Symbol Parameter
Processor
Min Typ Max Unit Notes
Core
Freq CPUID
Datasheet 33
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
18.This specification only applies to 1B GHz S-spec #: SL4WM. This part has a VID request of 1.70 V, however
the processor should be supplied 1.76 V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM.
19.This specification applies only to 1B GHz S-spec #: SL4WM. This value is 60 mV offset from the standard
specification and more at the Minimum specification. These tolerances are measured from a 1.70 V base,
while Vcc supplied is 1.76 V.
20. This processor exists in both FC-PGA and FC-PGA2.
2.10.1 ICC Slew Rate Specifications
This section contains typical current slew rate data for processors covered by this design guideline.
Actual slew rate values and wave-shapes may vary slightly depending on the type and size of
decoupling capacitors used in a particular implementation.
Figure 8. Slew Rate (23A Load Step)
Table 8. PL Slew Rate Data (23A) (Sheet 1 of 2)
Time (µs) ICC (A)
0.1 9.55
0.15 14.4
0.5 20.85
1 23.04
1.5 23.44
2 23.28
2.5 22.32
3 21.63
3.5 21.45
4 21.63
25
20
15
10
5
0
0.0E+00 1.0E-06 2.0E-06 3.0E-06 4.0E-06 5.0E-06
ICC (A)
Time (s)
Socket IP (23A, CPUID 068xh)
34 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All inputs, outputs, and I/O pins must comply with the signal quality specifications in Section 3.0.
3. Minimum and maximum VTT are given in Table 12 on page 36.
4. (0 ≤ VIN ≤ 1.5 V +3%) and (0≤VOUT≤1.5 V+3%).
5. Refer to the processor I/O Buffer Models for I/V characteristics.
6. Steady state input voltage must not be above VSS + 1.65 V or below VTT - 1.65 V.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Parameter measured at 9 mA (for use with TTL inputs).
3. (0 ≤ VIN ≤ 2.5 V +5%).
4. (0 ≤ VOUT ≤ 2.5 V +5%).
5. For BCLK specifications, refer to Table 24 on page 51.
6. (0 ≤ VIN ≤ 1.5 V +3%).
7. (0 ≤ VOUT ≤ 1.5 V +3%).
8. Applies to non-AGTL signals except BCLK, PICCLK, and PWRGOOD.
9. Applies to non-AGTL signals except BCLK, PICCLK, and PWRGOOD.
4.5 21.88
5 22.01
Table 9. AGTL / AGTL+ Signal Groups DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.150 VREF - 0.200 V 6
VIH Input High Voltage VREF + 0.200 VTT V 2, 3, 6
Ron Buffer On Resistance 16.67 Ω 5
IL
Leakage Current for inputs,
outputs, and I/O ±100 µA 4
Table 8. PL Slew Rate Data (23A) (Sheet 2 of 2)
Time (µs) ICC (A)
Table 10. Non-AGTL+ Signal Group DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL1.5 Input Low Voltage -0.150 VCMOS_REF -
0.200 V 9
VIL2.5 Input Low Voltage -0.58 0.700 V 5, 8
VIH1.5 Input High Voltage VCMOS_REF +
0.200 1.5 V 6, 9
VIH2.5 Input High Voltage 2.000 3.18 V 5, 8
VOL Output Low Voltage 0.400 V 2
Ron 35 2
VOH Output High Voltage 1.5 V 7, 9, All outputs are
open-drain
IOL Output Low Current 9 mA
ILI Input Leakage Current ±100 µA 3, 6
ILO Output Leakage Current ±100 µA 4, 7
Datasheet 35
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Parameter measured at 9 mA (for use with TTL inputs).
3. (0 ≤ VIN ≤ 2.5 V +5%); (0 ≤ VOUT ≤ 2.5 V +5%).
4. For BCLK specifications, refer to Table 24 on page 51.
5. (0 ≤ VIN ≤ 1.5 V +3%); (0 ≤ VOUT ≤ 1.5 V +3%).
6. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD.
7. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD.
8. For Coppermine-T differential clocking, the input low voltage is (VCMOS_REF - 0.300)V.
Table 11. Non-AGTL Signal Group DC Specifications 1
Symbol Parameter Min Max Unit Notes
VIL1.5 Input Low Voltage -0.150 VCMOS_REF -
0.300 V 7, 8
VIL2.5 Input Low Voltage -0.58 0.700 V 4, 6
VIH1.5 Input High Voltage VCMOS_REF +
0.200 1.5 V 5, 7
VIH2.5 Input High Voltage 2.000 3.18 V 4, 6
VOL Output Low Voltage 0.300 V 2
Ron 35 2
VOH Output High Voltage 1.5 V 5, 7, All outputs are
open-drain
IOL Output Low Current 9 mA
ILI Input Leakage Current ±100 µA 3, 5
ILO Output Leakage Current ±100 µA 3, 5
36 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.11 AGTL / AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT. These termination resistors are placed electrically between the ends of the signal
traces and the VTT voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called VREF. Refer to the appropriate platform design guide for more information
Table 12 below lists the nominal specification for the AGTL+ termination voltage (VTT). The
AGTL+ reference voltage (VREF) is generated on the system motherboard and should be set to 2/3
VTT for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the Intel® Pentium® II Processor Developer's Manual and AP-585,
Intel® Pentium® II Processor AGTL+ Guidelines.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. Pentium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. VTT and Vcc1.5 must be held to 1.5 V ±9%. It is required that VTT and Vcc1.5 be held to 1.5 V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. See
Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific
chipset/processor combination.
5. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
NOTES:
1. Specifications in this table do not apply to Pentium III processors at all frequencies. Please refer to the
Intel® Pentium® III Processor Specification Update for a complete listing on the processors that support the
AGTL specification.
2. Pentium III processors for the PGA370 socket contain AGTL termination resistors on the processor die,
except for the RESET# input.
3. VTT must be held to 1.25 V ±9%. It is required that VTT be held to 1.25 V ±3% while the processor system bus
is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard.
4. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. The
on-die RTT has a resistance tolerance of ±15%. See Section 7.0 for more details on the RTTCTRL signal.
Refer to the recommendation guidelines for the specific chipset/processor combination.
5. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
6. For the Coppermine-T differential clock platform, the on-die RTT min should be 50 Ω.
7. Coppermine-T UP platforms require a 56Ω resistor and Coppermine-T DP platforms require a 68Ω resistor.
Tolerance for the on-die RTT is ±10% for 56Ω and 68Ω resistors and ±15% for 100 Ω resistors
Table 12. Processor AGTL+ Bus Specifications 1, 2
Symbol Parameter Min Typ Max Units Notes
VTT Bus Termination Voltage 1.50 V 3
On-die RTT Termination Resistor 40 130 Ω 4
VREF Bus Reference Voltage 0.950 2/3 VTT 1.05 V 5
Table 13. Processor AGTL Bus Specifications 1, 2
Symbol Parameter Min Typ Max Units Notes
VTT Bus Termination Voltage 1.14 1.25 1.308 V 3
On-die RTT Termination Resistor 506 56, 68 115 Ω 4, 7
VREF Bus Reference Voltage 2/3 VTT - 2% 2/3 VTT 2/3 VTT + 2% V 5
Datasheet 37
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.12 System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0 for the processor signal definitions.
Table 14 through Table 20 list the AC specifications associated with the processor system bus.
These specifications are placed into the following categories: Table 14 and Table 15 contain the
system bus clock specifications, Table 16 contains the AGTL+/AGTL specifications, Table 17
contains the CMOS signal group specifications, Table 18 contains timings for the reset conditions,
Table 19 and covers APIC bus timing, and Table 20 covers power on timing.
All processor system bus AC specifications for the AGTL+/AGTL signal group are relative to the
rising edge of the BCLK input. All AGTL+/AGTL timings are referenced to VREF for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in the FC-PGA package in Viewlogic* XTK/XNS* model format
(formerly known as QUAD format) and IBIS * 3.1 format as the Pentium III Processor for the
PGA370 Socket I/O Buffer Models (Electronic Format).
AGTL and AGTL+ layout guidelines are also available in the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
2.12.1 I/O Buffer Model
An electronic copy of the I/O Buffer Model for the AGTL+ and CMOS signals is available at
Intel’s Developer’s Website (http://developer.intel.com). The model is for use in single processor
designs and assumes the presence of motherboard RTT values as described in Table 12 on page 36.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.
Table 14. System Bus AC Specifications (SET Clock)1, 2
T# Parameter Min Nom Max Unit Figure Notes
System Bus Frequency
100.00
133.33
MHz 4
T1: BCLK Period
10.0
7.5
ns 9
4, 5, 10
4, 5, 11
T2: BCLK Period Stability
±250
±250
ps
6, 7, 10
6, 7, 11
T3: BCLK High Time
2.5
1.4
ns 9
9, 10
9, 11
T4: BCLK Low Time
2.4
1.4
ns 9
9, 10
9, 11
T5: BCLK Rise Time 0.4 1.6 ns 9 3, 8
T6: BCLK Fall Time 0.4 1.6 ns 9 3, 8
38 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3. Not 100% tested. Specified by design characterization as a clock driver requirement.
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 MHz or 133 MHz, not both.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5 V–2.0 V. BCLK fall time is measured between 2.0 V–0.5 V.
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
time below 0.5 V.
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz.
11.This specification applies to Pentium III processors operating at a system bus frequency of 133 MHz
NOTES:
1. Measurement taken from differential waveform, defined as BCLK - BCLK#.
2. Period is defined from one rising 0 V-crossing to the next.
3. Measurement taken from differential waveform, voltage range from -0.35 V to +0.35 V.
4. Measurement taken from common mode waveform, measure rise/fall time from 0.41 V to 0.86 V. Rise/fall
time matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum
BCLK# fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time. “This parameter is
designed to guard waveform symmetry.
5. Period difference measured around 0 V-crossings; measurement taken from differential waveform.
6. The rising and falling edge ringback voltage specified is the minimum (rising) or them maximum (falling)
voltage, the differential waveform can go after passing Vih_diff (rising) or Vil_diff (falling)
7. Measured in absolute voltage, i.e. single-ended measurement. Includes every cross point for both rise and
fall of BCLK.
8. Input high or input low voltage range measured in absolute voltage, i.e. single-ended measurement.
9. The internal Core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency 133 MHz. Table 16 shows supported ratios for each processor
10.Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 pF to 20 pF. The jitter
must be accounted for as a component of BCLK timing skew between devices.
11.AC parameters are measured at the processor pins.
12.BCLK/BCLK# must rise/fall monotonically between Vil and Vih.
Table 15. System Bus Timing Specifications (Differential Clock)1, 11, 12
Parameter
133 MHz 100 MHz
Units Notes
Min Max Min Max
Clock Period—Average 7.5 7.7 10.0 10.2 ns 2, 9, 10
Instantaneous Minimum Clock Period 7.30 9.8 ns 2, 9, 10
CLK Differential Rise Time 175 550 175 467 ps 1, 3
CLK Differential Fall Time 175 550 175 467 ps 1, 3
Waveform Symmetry 325 325 ps 4
Differential Cycle to Cycle Jitter 200 200 ps 1, 5
Differential Duty Cycle 45% 55% 45% 55% 1
Rising Edge Ring Back 0.35 0.35 V 1, 6
Falling Edge Ring Back –0.35 –0.35 V 1, 6
Cross Point at 1V 0.51 0.76 0.51 0.76 V 7
Input High Voltage 0.92 1.45 0.92 1.45 V 8
Input Low Voltage –0.2 0.35 –0.2 0.35 V 8
Datasheet 39
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pins (for
AGTL, the timings are referenced to the rising edge of BCLK and the falling edge of BCLK# at the processor
pins). All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V (2/3 VTT for AGTL) at the
processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.5 V, VREF at 1.0 V ±2% and with 56 Ω on-die
RTT. For AGTL platforms, the valid delay timings are specified into 50 Ω to 1.25 V, VREF at 2/3 VTT ±2% and
with 56 Ω on-die RTT.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
7. Specification is for a minimum 0.40 V swing from VREF - 200 mV to VREF + 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V (2/3 VTT for AGTL) swing from VTT - 1V to VTT. This assumes an edge
rate of 3V/ns.
9. This should be measured after VCCCORE, VTT, VccCMOS, and BCLK become stable.
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11.This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
13.For AGTL, VREF is 2/3 VTT ±3%.
Table 16. System Bus AC Specifications (AGTL+ or AGTL Signal Group)1, 2, 3, 13
T# Parameter Min Max Unit Figure Notes
T7: AGTL+ Output Valid Delay 0.40 3.25 ns 11 4, 10, 11
T8: AGTL+ Input Setup Time
1.20
0.95
ns
ns
12
12
5, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time 1.00 ns 12 8, 10
T10: RESET# Pulse Width 1.00 ms 13 6, 9, 10
40 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK become stable.
NOTE: 1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
NOTES:
Table 17. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter Min Max Unit Figure Notes
T14: CMOS Input Pulse Width, except
PWRGOOD 2 BCLKs 11 Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width 10 BCLKs 11, 14 5
Table 18. System Bus AC Specifications (Reset Conditions) 1
T# Parameter Min Max Unit Figure Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time 4 BCLKs 13 Before deassertion
of RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time 2 20 BCLKs 13 After clock that
deasserts RESET#
Table 19. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter Min Max Unit Figure Notes
T21: PICCLK Frequency 2.0 33.3 MHz
T22: PICCLK Period 30.0 500.0 ns 9
T23: PICCLK High Time 10.5 ns 9 @ > 1.7V
T24: PICCLK Low Time 10.5 ns 9 @ < 0.7V
T25: PICCLK Rise Time 0.25 3.0 ns 9 (0.7V - 1.7V)
T26: PICCLK Fall Time 0.25 3.0 ns 9 (1.7V - 0.7V)
T27: PICD[1:0] Setup Time 5.0 ns 12 4
T28: PICD[1:0] Hold Time 2.5 ns 12 4
T29a: PICD[1:0] Valid Delay (Rising Edge) 1.5 8.7 ns 10, 11 4, 5, 6
T29b: PICD[1:0] Valid Delay (Falling Edge) 1.5 12.0 ns 10, 11 4, 5, 6
Table 20. Platform Power-On Timings2
T# Parameter Min Max Unit Figure Notes
T45: Valid Time Before VTT_PWRGD 1.0 mS 14 1
T46: Valid Time Before PWRGOOD 2.0 mS 14 1
T47: RESET# Inactive to Valid Outputs 1 BCLK 14 1
T48: RESET# Inactive to Drive Signals 4 BCLK 14 1
Datasheet 41
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
during processor power-up sequence.
2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to
Table 17 and Figure 13.
Note: For Figure 9 through Figure 15, the following apply:
1. Figure 9 through Figure 15 are to be used in conjunction with Table 14 through Table 20.
2. All AC timings for the AGTL+ signals at the processor pins are referenced to the BCLK rising
edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V
at the processor pins.
3. All AC timings for the APIC I/O signals at the processor pins are referenced to the PICCLK
rising edge at 1.25 V. All APIC I/O signal timings are referenced at 0.75 V at the processor
pins.
4. All AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge
at 0.75 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor
pins.
Figure 9. Generic Clock Waveform
V ih
BCLK#
BCLK
V il
V cross
Tp
T p = T 1 (BCLK Perio d )
NO TE: Sin g le -Ended c lock uses BC LK on ly,
Differe n tial clock uses BLCK and BC LK#
42 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 10. BCLK, PICCLK, and TCK Generic Clock Waveform
Figure 11. System Bus Valid Delay Timings
V3
V1
V2
Tp
Tl
Th
Tr Tf
Vringback
(rise)
Vringback
(fall)
Tr = T5, T25, T34, (Rise Time)
Tf = T6, T26, T35, (Fall Time)
Th = T3, T23, T32, (High Time)
Tl = T4, T24, T33, (Low Time)
Tp = T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK is referenced to 0.30V (Differential Mode), 0.50V (Single-Ended Mode)
TCK is referenced to Vref - 200 mV, PICCLK is referenced to 0.4V.
V2 = BCLK is refernced to 0.9V (Differental Mode), 2.0V (Single-Ended Mode)
TCK is referenced to Vref + 200 mV, PICCLK is refernced to 1.6V
V3 = BCLK and BLCK# crossing point of the rising edge of BLCK and the falling edge of BCLK# (Differential Mode),
BCLK i refereced to 1.25V (Single-Ended Mode), PICCLK is reference to 1.0V, TCK is referenced to Vcmosref
0V
Vih diff
Vil diff
BCLK
Signal
Valid
Tx
V
Tx
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups
BCLK#
Valid
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
Datasheet 43
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 12. System Bus Setup and Hold Timings
Figure 13. System Bus Reset and Configuration Timings
BCLK
Valid
Ts
V
Th
VCross = Crossing point of BLCK and BCLK#
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups
VCross
BCLK#
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
T9 = (AGTL+ Input Hold Time)
T8 = (AGTL+ Input Setup Time)
T10 = (RESET# Pulse Width)
T16 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time)
T17 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
BCLK
RESET#
Configuration
(A[14:5]#, BR0#,
BR1#, FLUSH#,
INT#)
BCLK#
Valid
T10
T16
T17
T8
T9
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
44 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 14. Platform Power-On Sequence Timings
Vtt, Vref
Vcmosref
Valid
Valid
VID
BSEL[1:0]
T45
VTT_PWRGD
VCC_Core
PICCLK
BCLK#
BCLK
Valid Config Active Inactive
Valid
Valid
Valid
Valid
Active
T46
T47
T48
VCC_PWRGD
Configuration Inputs
RESET#
THERMTRIP#
PICD[1:0]
AGTL Outputs
All other CMOS
Outputs
Inactive All other Inputs
Datasheet 45
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 15. Power-On Reset and Configuration Timings
Ta
Valid Ratio
TC
Tb
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Ta = T15 (PWRGOOD Inactive Pulse)
Tb = T10 (RESET# Pulse Width)
Tc = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
765a
BCLK
VIL, max
VIH, min
VccCORE, VTT,
VREF
46 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.0 Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 21, Table , Table 23, Table , and Table
ensures that signal quality effects will not adversely affect processor operation.
3.1 BCLK/BCLK# and PICCLK Signal Quality Specifications
and Measurement Guidelines
Table 21 describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals. Figure 16 describes the signal quality
waveform for the system bus clock at the processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors that support the AGTL
specification. Refer to the Intel® Pentium® III Processor Specification Update for a complete listing on the
processors that support the AGTL specification.
Table 21. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins 1
T# Parameter Min Nom Max Unit Figure Notes
V1: BCLK VIL 0.500 V 16
V1: PICCLK VIL 0.700 V 16
V2: BCLK VIH 2.000 V 16
V2 PICCLK VIH 2.000 V 16
V3: VIN Absolute Voltage Range –0.58 3.18 V 16
V4: BCLK Rising Edge Ringback 2.000 V 16 2
V4: PICCLK Rising Edge Ringback 2.000 V 16 2
V5: BCLK Falling Edge Ringback 0.500 V 16 2
V5: PICCLK Falling Edge Ringback 0.700 V 16 2
Table 22. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins in
a Differential Clock Platform for AGTL
T# Parameter Min Nom Max Unit Figure Notes
V1: PICCLK VIL 0.40 V 16
V2 PICCLK VIH 1.60 V 16
V3: PICCLK Absolute Voltage
Range -0.4 2.4 V 16
V4: PICCLK Rising Edge Ringback 1.60 V 16 2
V5: PICCLK Falling Edge Ringback 0.40 V 16 2
Datasheet 47
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
3.2 AGTL+ / AGTL Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guide. Refer to the Intel® Pentium® II Processor
Developer's Manual (Order Number 243502) for the AGTL+/AGTL buffer specification.
Table 23 provides the AGTL+ signal quality specifications for the processor for use in simulating
signal quality at the processor pins.
The Pentium III processor for the PGA370 socket maximum allowable overshoot and undershoot
specifications for a given duration of time are detailed in Table 25 through Table 27. Figure 17
shows the AGTL+/AGTL ringback tolerance and Figure 18 shows the overshoot/undershoot
waveform.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See Figure 17 for the generic waveform.
3. All values specified by design characterization.
4. Please see Table 25 for maximum allowable overshoot.
5. Ringback between VREF + 100 mV and VREF + 200 mV or VREF - 200 mV and VREF - 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel®Pentium®II
Developers Manual). Ringback below VREF + 100 mV or above VREF - 100 mV is not supported.
Figure 16. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V2
V1
V3
V3
V4
V5
Table 23. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins 1, 2, 3
T# Parameter Min Unit Figure Notes
α: Overshoot 100 mV 17 4, 8
τ: Minimum Time at High 0.50 ns 17
ρ: Amplitude of Ringback ±200 mV 17 5, 6, 7, 8
φ: Final Settling Voltage 200 mV 17 8
δ: Duration of Squarewave Ringback N/A ns 17
48 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
sources of system noise.
7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = -100 mV specifies the
signal cannot ringback below VREF + 100 mV).
8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200mV.
3.3 AGTL+ Signal Quality Specifications and Measurement
Guidelines
3.3.1 Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the Pentium III processor performance, care must be taken to ensure
that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will
impact results and may yield excessive overshoot/undershoot.
Figure 17. Low to High AGTL+ Receiver Ringback Tolerance
0.7V Clk Ref
Clock
Time
Vstart
VREF - 0.2
VREF
VREF + 0.2
Note: High to low case is analogous
τ
α
δ
ρ
φ
Datasheet 49
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.3.2 Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This could be accomplished by simultaneously measuring the VTT plane while measuring the
signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform. The
true undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT - Signal_measured
Note: The converted undershoot waveform appears as a positive (overshoot) signal.
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
After the true waveform conversion, the undershoot/overshoot specifications shown in Table 25
through Table 27 can be applied to the converted undershoot waveform using the same magnitude
and pulse duration specifications used with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in Table 25 through Table 27. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must
all be used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3 Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.635 V). The total time could encompass several
oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
Note: Oscillations below the reference voltage cannot be subtracted from the total overshoot/undershoot
pulse duration.
Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that
total event.
3.3.4 Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The specifications provided in Table 25 through Table 27 show the Maximum Pulse Duration
allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each Table
entry is independent of all others, meaning that the Pulse Duration reflects the existence of
overshoot/undershoot events of that magnitude only. A platform with an overshoot/undershoot that
50 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be
NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the
event occurs at all times and no other events can occur).
Note: Activity factor for AGTL+ signals is referenced to BCLK frequency.
Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
3.3.5 Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Pentium III processor for the PGA370 socket is not
a simple single value. Instead, many factors are needed to determine what the over/undershoot
specification is. In addition to the magnitude of the overshoot, the following parameters must also
be known: the junction temperature the processor will be operating at, the width of the overshoot
(as measured above 1.635 V) and the Activity Factor (AF). To determine the allowed overshoot for
a particular overshoot event, the following must be done:
1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal
operating with a 100 MHz system bus, use Table 25 (100MHz AGTL+ signal group). If the
signal is an AGTL+ signal operating with a 133MHz system bus, use Table 26 (133 MHz
AGTL+ signal group). If the signal is a CMOS signal, use Table 27 (33 MHz CMOS signal
group).
2. Determine the maximum junction temperature (Tj) for the range of processors that the system
will support (80oC or 85oC).
3. Determine the Magnitude of the overshoot (relative to VSS)
4. Determine the Activity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Below is an example showing how the maximum pulse duration is determined for a given
waveform.
NOTES:
1. Corresponding Maximum Pulse Duration Specification - 2.4 ns
2. Pulse Duration (measured) - 2.0 ns
Given the above parameters, and using Table 26 (85 oC/AF = 0.1 column) the maximum allowed
pulse duration is 2.4 ns. Since the measure pulse duration is 2.0 ns, this particular overshoot event
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
Table 24. Example Platform Information
Required Information Maximum Platform Support Notes
FSB Signal Group 133 MHz AGTL+
Max Tj 85 °C
Overshoot Magnitude 2.13V Measured Value
Activity Factor (AF) 0.1 Measured overshoot occurs on
average every 20 clocks
Datasheet 51
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.3.6 Determining if a System Meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
you add the total impact of all overshoot events, the system may fail. A guideline to ensure a
system passes the overshoot and undershoot specifications is shown below. It is important to meet
these guidelines; otherwise, contact your Intel field representative.
1. Insure no signal (CMOS or AGTL+/AGTL) ever exceed the 1.635 V
OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables
OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 25 through Table 27.
NOTES:
1. Overshoot/Undershoot Magnitude = 2.18 V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to VSS.
3. Undershoot is measured relative to VTT
4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V.
5. Ringbacks below VTT can not be subtracted from Overshoots/Undershoots
6. Leser Undershoot does not allocate longer or larger Overshoot
7. OEM's are encouraged to follow Intel provided layout guidelines. Consult the layout guidelines
provided in the specific platform design guide.
8. All values specified by design characterization
NOTES:
1. BCLK period is 10 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 25. 100 MHz AGTL+ / AGTL Signal Group Overshoot/Undershoot Tolerance at
Processor Pins1,2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 20 2.53 0.25 18.6 1.86 0.18
2.13 V 20 4.93 0.49 20 3.2 0.32
2.08 V 20 9.1 0.91 20 6.1 0.6
2.03 V 20 16.6 1.67 20 11.4 1.1
1.98 V 20 20 3.0 20 20 2
1.93 V 20 20 5.5 20 20 6.6
1.88 V 20 20 10 20 20 20
52 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. BCLK period is 7.5 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
NOTES:
1. PICCLK period is 30 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Table 26. 133 MHz AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance 1, 2
Overshoot/Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80
°C (ns)
Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 15 1.9 0.19 14 1.4 0.14
2.13 V 15 3.7 0.37 15 2.4 0.24
2.08 V 15 6.8 0.68 15 4.6 0.46
2.03 V 15 12.5 1.25 15 8.6 0.84
1.98 V 15 15 2.28 15 15 1.5
1.93 V 15 15 4.1 15 15 5
1.88 V 15 15 7.5 15 15 15
Table 27. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins1, 2
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 85 °C
(ns)
AF = 0.01 AF = 0.1 AF = 1 AF = 0.01 AF = 0.1 AF = 1
2.18 V 60 7.6 0.76 56 5.6 0.56
2.13 V 60 14.8 1.48 60 9.6 0.96
2.08 V 60 27.2 2.7 60 18.4 1.8
2.03 V 60 50 5 60 33 3.3
1.98 V 60 60 9.1 60 60 6
1.93 V 60 60 16.4 60 60 20
1.88 V 60 60 30 60 60 60
Datasheet 53
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 18. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
Figure 19. Maximum Acceptable AGTL Overshoot/Undershoot Waveform
Vss
Undershoot
Magnitude
= VTT - Signal
Overshoot
Magnitude
= Signal - Vss
VTT
2.18V
2.08V
1.98V
1.88V
1.635V
Max
Overshoot
Magnitude
Time Dependent
Overshoot
Converted Undershoot
Waveform
Undershoot
Magnitude
Time Dependent
Undershoot
Vos_ref
1.78V Max
1.32V
Vss
Time dependent Overshoot
Time dependent Undershoot
-.46V Min
α β χ
α β χ
.1ns
.3ns
1ns
.1ns .3ns 1ns
1.47V
1.62V
-.15V
-.30V
54 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.4 Non-AGTL+ (Non-AGTL) Signal Quality Specifications and
Measurement Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in Figure 20 for the non-
AGTL+ signal group.
NOTES:
1. VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. VHI = 2.5 V for BCLK,
PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.
3.4.1 Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates (see Figure 20 for non-AGTL+ signals). The processor can be damaged by
repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if
the overshoot is great enough). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the
ringback specification difficult. The overshoot/undershoot guideline is 0.3 V and assumes the
absence of diodes on the input. These guidelines should be verified in simulations without the onchip
ESD protection diodes present because the diodes will begin clamping the 1.5 V and 2.5 V
tolerant signals beginning at approximately 0.7 V above the appropriate supply and 0.7 V below
VSS. If signals are not reaching the clamping voltage, this will not be an issue. A system should not
rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the
components and make meeting the ringback specification very difficult.
Note: The undershoot guideline limits transitions exactly as described for the ATGL+/AGTL signals. See
Figure 18.
Figure 20. Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and Ringback 1
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Falling-Edge
Ringback
VLO
VSS Time
VHI
Datasheet 55
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.4.2 Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See Figure 20 for an illustration of ringback. Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ (non-AGTL) signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL+ signals except PWRGOOD.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL signals except PWRGOOD.
3. For Coppermine-T with differential clocking, this signal is 1.8 V tolerant.
3.4.3 Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total signal swing (VHI –VLO) above
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
Table 28. Signal Ringback Specifications for Non-AGTL+ Signal Simulations at the Processor
Pins1
Input Signal Group Transition Maximum Ringback
(with Input Diodes Present) Unit Figure
Non-AGTL+ Signals 2 0 →1 VCMOS_REF + 0.200 V 20
Non-AGTL+ Signals 2 1 →0 VCMOS_REF - 0.200 V 20
PWRGOOD 0 →1 2.00 V 20
Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulations at the Processor
Pins 1
Input Signal Group Transition Maximum Ringback
(with Input Diodes Present) Unit Figure
Non-AGTL+ Signals 2 0 →1 VCMOS_REF + 0.200 V 20
Non-AGTL+ Signals 2 1 →0 VCMOS_REF - 0.300 V 20
PWRGOOD 0 →1 2.00 3 V 20
56 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz
4.0 Thermal Specifications and Design Considerations
This chapter provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design
Guidelines (Document Number 245087). The Pentium III processor uses flip chip pin grid array
packaging technology and has a junction (Tjunction) or case temperature (Tcase) specified.
4.1 Thermal Specifications
Table 30 provides the thermal design power dissipation and maximum temperatures for the
Pentium III processor for the PGA370 socket. Systems should design for the highest possible
processor power, even if a processor with a lower thermal dissipation is planned. A thermal
solution should be designed to ensure the junction temperature never exceeds these specifications.
NOTES:
1. These values are specified at nominal VCCCORE for the processor pins.
Table 30. Intel® Pentium® III Processor Thermal Design Power for the FC-PGA Package1
Processor
Processor
Core
Frequency
(MHz)
System
Bus
Frequency
(MHz)
Processor
Thermal
Design
Power 2,3
up to
CPUID
0686h
(W)
Processor
Thermal
Design
Power 2,3
CPUID
068Ah
(W)
Power
Density5
for
CPUID
068Ah
(W/cm2)
Maximum
TJUNCTION
10
(°C)
TJUNCTION
Offset for
Latest
Stepping
4,6
(°C)
500E 500 100 13.2 N/A N/A 85 1.9
533EB 533 133 14.0 N/A N/A 85 2.0
550E 550 100 14.5 N/A N/A 85 2.1
600E 600 100 15.8 19.6 30.5 82 2.6
600EB 600 133 15.8 N/A N/A 82 2.3
650 650 100 17.0 N/A N/A 82 2.7
667 667 133 17.5 N/A N/A 82 2.8
700 700 100 18.3 21.9 34.1 80 2.9
733 733 133 19.1 22.8 35.5 80 3.0
750 750 100 19.5 23.2 36.1 80 3.0
800 800 100 20.8 24.5 38.2 80 3.2
800EB 800 133 20.8 24.5 38.2 80 3.2
850 850 100 22.5 25.7 40.0 80 3.4
866 866 133 22.9 26.1 40.7 80 3.4
900 900 100 23.2 26.7 41.6 77 3.5
933 933 133 24.5 27.5 42.8 77 3.6
1 GHz 1000 100 N/A 29.0 45.2 758 3.8
1B GHz 1000 133 26.1 29.0 45.2 709 758 3.8
1B GHz7 1000 133 29.6 N/A N/A 70 3.9
1.10 GHz 1100 100 N/A 33.0 51.4 77 4.4
Datasheet 57
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tjunction specification.
3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to
Table 6 for voltage regulation and electrical specifications.
4. Tjunctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the
hottest location on the processor’s core.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in Figure 21.
6. TJUNCTION offset values do not include any thermal diode kit measurement error. Diode kit measurement
error must be added to the TJUNCTION offset value from the table, as outlined in the Intel® Pentium® III
processor Thermal Metrology for CPUID-068h Family Processors (Order Number: 245301). Intel has
characterized the use of the Analog Devices AD1021 diode measurement kit and found its measurement
error to be 1 °C.
7. This specification only applies to 1B GHz S-Spec #: SL4WM. This part has a VID request of 1.70 V, however
the processor should be supplied 1.76 V at the PGA Vcc pins by the VRM (Voltage Regulator Module) or by
the voltage regulator circuit.
8. This specification applies to processors with CPUID 068AH. 1B GHz exists in both FC-PGA and FC-PGA2
packages.
9. This specification applies to processors with CPUID 0686H.
10. Tjunction minimum specification is 0 °C.
Table 31 provides the thermal design power dissipation and maximum temperatures for the
Pentium III processor for the FC-PGA2 package. Systems should design for the highest possible
processor power, even if a processor with a lower thermal dissipation is planned. A thermal
solution should be designed to ensure the case temperature never exceeds these specifications.
NOTES:
1. These values are specified at nominal VCCCORE for the processor pins.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tcase specification.
3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to
Table 7 for voltage regulation and electrical specifications.
4. TCaseOffset is the worst-case difference between the maximum case temperature and the thermal diode
temperature on the processor’s core. For more information please refer to the document, Intel® Pentium® III
Processor in the FC-PGA2 Package Thermal Design Guide.
5. This processor exists in both FC-PGA and FC-PGA2 packages.
4.2 Processor Die Area
Figure 21 is a block diagram of the Pentium III processor die layout and Table 32 contains Pentium
III processor die layout measurements. The layout differentiates the processor core from the cache
die area. In effect, the thermal design power identified in Table 30 is dissipated entirely from the
processor core area. Thermal solution designs should compensate for this smaller heat flux area
and not assume that the power is uniformly distributed across the entire die area.
Table 31. Intel® Pentium® III Processor for the FC-PGA2 Package Thermal Design Power 1
Processor
Processor
Core
Frequency
(MHz)
System Bus
Frequency
(MHz)
Processor
Thermal Design
Power 2,3
CPUID 068Ah
(W)
Maximum
Tcase
4
(°C)
Additional
Notes
866 866 133 29.5 70 5
933 933 133 31.5 72 5
1B GHz 1000 133 33.9 69 5
1.13 GHz 1133 133 37.5 72
58 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz
4.3 Thermal Diode
The Pentium III processor for the PGA370 socket incorporates an on-die diode that may be used to
monitor the die temperature (junction temperature). A thermal sensor located on the motherboard,
or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal
management or instrumentation purposes. Table 33 and Table 34 provide the diode parameter and
interface specifications. For more information please refer to the document, Intel® Pentium® III
Processor in the FC-PGA2 Package Thermal Design Guide.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, ondie
temperature gradients between the location of the thermal diode and the hottest location on the
die at a given point in time, and time based variations in the die temperature measurement. Time
based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is
slower than the rate at which the Tjunction temperature can change.
Figure 21. Processor Functional Die Layout for FC-PGA
Table 32. Processor Functional Die Layout for FC-PGA
CPUID A: Die Area (cm2) B: Core Area (cm2) C: Cache Area (cm2)
0683H 1.046 0.726 0.320
0686H 0.900 0.642 0.258
068AH 0.947 0.642 0.305
A: Die Area
B: Core Area (~63% of die area)
C: Cache Area
Pin 1
Product Label
Datasheet 59
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.10 GHz
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 100 ° C with a forward bias current of 5 µA–300 µA.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
Ifw=Is(e^ ((Vd*q)/(nkT)) - 1), where Is = saturation current, q = electronic charge, Vd = voltage across the
diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4. Not 100% tested. Specified by design characterization.
Table 33. Thermal Diode Parameters1
Symbol Parameter Min Typ Max Unit Notes
Ifw Forward Bias Current 5 300 µA 1
n Diode Ideality Factor 1.0057 1.0080 1.0125 2, 3, 4
Table 34. Thermal Diode Interface
Pin Name PGA370 Socket pin # Pin Description
THERMDP AL31 diode anode (p_junction)
THERMDN AL29 diode cathode (n_junction)
60 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
5.0 Mechanical Specifications
The Pentium III processor uses a FC-PGA and FC-PGA2 package technology. Mechanical
specifications for the processor are given in this section. FC-PGA2 contains an Integrated Heat
Spreader (IHS) to spread out the heat generated from the die. See Section 1.1.1 for a complete
terminology listing.
The processor utilizes a PGA370 socket for installation into the motherboard. Details on the socket
are available in the 370-Pin Socket (PGA370) Design Guidelines.
Note: For Figure 23 and Figure 24 the following apply:
1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production
product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational
purposes only. Reference dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference dimensions are
NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in
parentheses without tolerances are reference dimensions.
4. Drawings are not to scale.
The following figure with package dimensions is provided to aid in the design of heatsink and clip
solutions as well as demonstrate where pin-side capacitors will be located on the processor.
Table 35 includes the measurements for these dimensions in both inches and millimeters.
5.1 FC-PGA Mechanical Specifications
The following figure with package dimensions is provided to aid in the design of heatsink and clip
solutions as well as demonstrate where pin-side capacitors will be located on the processor.
Table 35 includes the measurements for these dimensions in both inches and millimeters.
Figure 22. FC-PGA and FC-PGA2 Package Types
FC-PGA2 FC-PGA
Datasheet 61
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTE: Capacitors will be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and
G3. This area is a keepout zone for motherboard designers.
Figure 23. Package Dimensions
Table 35. Intel® Pentium® III Processor Package Dimensions
Symbol
Millimeters Inches
Minimum Maximum Notes Minimum Maximum Notes
A1 0.787 0.889 0.031d 0.035
A2 1.000 1.200 0.039 0.047
B1 11.226 11.329 0.442 0.446
B2 9.296 9.398 0.366 0.370
C1 23.495 max 0.925 max
C2 21.590 max 0.850 max
D 49.428 49.632 1.946 1.954
D1 45.466 45.974 1.790 1.810
G1 0.000 17.780 0 0.700
G2 0.000 17.780 0 0.700
G3 0.000 0.889 0 0.035
H 2.540 Nominal 0.100 Nominal
L 3.048 3.302 0.120 0.130
ΦP 0.431 0.483 Pin Diameter 0.017 0.019
Pin TP 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin)
62 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The bare processor die has mechanical load limits that should not be exceeded during heat sink
assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach
solution must not induce permanent stress into the processor substrate with the exception of a
uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and
static loading parameters are listed in Table 36.
For Table 36, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads.
NOTES:
1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
3. Please see socket manufacturer’s force loading specification also to ensure compliance.
Table 36. Processor Die Loading Parameters for FC-PGA
Parameter Dynamic (max)1 Static (max)2 Unit Added
Notes
Silicon Die Surface 200 50 lbf 3
Silicon Die Edge 100 12 lbf 3
Datasheet 63
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
5.1.1 FC-PGA2 Mechanical Specifications
The following figure is provided to aid in the design of heatsink and clip solutions. Also, it is used
to demonstrate where pin-side capacitors will be located on the processor. Table 31 includes the
measurements for these dimensions in both inches and millimeters.
Figure 24. Package Dimensions for FC-PGA2
Table 37. Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package
Symbol
Millimeters Inches
Minimum Maximum Notes Minimum Maximum Notes
A1 2.266 2.690 0.089 0.106
A2 0.980 1.180 0.038 0.047
B1 30.800 31.200 1.212 1.229
B2 30.800 31.200 1.212 1.229
C1 33.000 max 1.299 max
C2 33.000 max 1.299 max
D 49.428 49.632 1.946 1.954
D1 45.466 45.974 1.790 1.810
G1 0.000 17.780 0.000 0.700
G2 0.000 17.780 0.000 0.700
G3 0.000 0.889 0.000 0.035
H 2.540 Nominal 0.100 Nominal
L 3.048 3.302 0.120 0.130
ΦP 0.431 0.483 0.017 0.019
64 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTE: Capacitors will be placed on the pin-side of the FC-PGA package in the area defined by G1, G2, and
G3. This area is a keepout zone for motherboard designers.
For Table 38, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads
NOTES:
1. Transient loading refers to a one time short duration loading, such as during heatsink installation.
2. Dynamic loading refers to a shock load.
3. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
4. Please see socket manufacturer’s force loading specification also to ensure compliance. Maximum static
loading listed here does not account for the maximum reaction forces on the socket tabs or pins. Designs
must ensure that the socket can withstand this force.
Pin TP 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin)
Table 37. Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package
Symbol
Millimeters Inches
Minimum Maximum Notes Minimum Maximum Notes
Table 38. Processor Case Loading Parameters for FC-PGA2
Parameter Transient
(max)1, 4
Dynamic
(max)2, 4
Static
(max)3, 4 Unit
IHS Surface 200 200 100 lbf
IHS Edge 125 N/A N/A lbf
IHS Corner 75 N/A N/A lbf
Figure 25. FC-PGA2 Flatness Specification
Note: Flatness specifications in millimeters
Datasheet 65
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
5.2 Processor Markings
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium III processor for the PGA370 socket. Table 35 and Table 37 list the
measurements for the package dimensions.
5.2.1 Processor Markings for FC-PGA2
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium III processor for the FC-PGA2 socket. Table 37 lists the measurements
for the package dimensions. (Note: this package label will also have a 2D matrix mark.)
Figure 26. Top Side Processor Markings for FC-PGA (up to CPUID 0x686H)
Figure 27. Top Side Processor Markings for FC-PGA (for CPUID 0x68AH))
Dynamic Production Mark Example
RB80526PY550266
FFFFFFFF-0001 SSSSS
FPO # - S/N S-spec#
pentium III logo
MALAY intel ®
i (m) (c) ’99
Static Mark ink printed at
substrate supplier Country of Origin
Dynamic Laser Mark
Swatch
Product Code
GRP1LN1: INTEL (m)(c) '01_-_{COO}
GRP1LN2: {Speed}/{Cache}/{Bus}/{Voltage}
GRP2LN1: {FPO}-{S/N}
GRP2LN2: PENTIUM III {S-Spec}
66 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
5.3 Recommended Mechanical Keep-Out Zones
NOTES:
1. This drawing applies to FC-PGA2 package. The only differences from the FC-PGA package Keep-Out
drawing are as follows: height 2.160” was changed from 2.100” and height 1.118” was changed from 1.058”.
2. Refer to the Pentium III Thermal/Mechanical Solution Functional Guidelines (see section 1.2 for reference
order number) for the latest information.
Figure 28. Top Side Processor Markings for FC-PGA2
Figure 29. Volumetric Keep-Out for FC-PGA and FC-PGA2 1, 2
GRP2LN1
GRP2LN2
GRP1LN1
GRP1LN2 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin}
GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1: {FPO}-{S/N}
GRP2LN2: PENTIUM III {S-Spec}
Datasheet 67
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
5.4 Processor Signal Listing
Table 39 and Table 40 provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 31 provides a pin-side view of the Pentium III processor pinout.
Figure 30. Component Keep-Out
Datasheet 68
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 31. Intel® Pentium® III Processor Pinout
pinout
VSS
VCC
VSS D35
D29
D33
D26
D28
D21 D23
D25
VSS
VCC
VSS
D31
VCC
D43
VCC VSS
D34
D38
VCC VSS
D39
D36
VCC
D37 D44
VCC VCC D32 D22 RSV D27
VSS
D42
D45 D49
VSS
VCC D63 VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS
VCC VSS VCC VSS RSV VTT D62 SLEW
CTRL
DEP6 DEP4 VREF0 BPM1 BP3
D41 D52 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
D40 D59 D55 D54 D58 D50 D56 DEP5 DEP1 DEP0 BPM0 CPUPRES
VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BINIT
D51 D47 D48 D57 D46 D53 D60 D61 DEP7
Dep7
DEP3 DEP2 PRDY VSS
BP2 VTT RSV
VCC VSS VCC
PICCLK PICD0 PREQ
VCC VCC VSS
RSV PICD1 LINT1
VCC VSS LINT0
RSV RSV RSV
VSS VCC VSS
RSV RSV RSV
VCC VSS VCC
VTT RTT
CTRL
VTT
VSS VCC VSS
PLL2 VTT VTT
VCC VSS VCC
CLKREF VCC VSS
VCC VSS V_2.5
VTT VTT VCC
VSS VCC V_CMOS
VSS FERR RSP
VCC VSS V_1.5
A20M IERR FLUSH
VSS VCC VSS
INIT
VSS VCC VSS
PLL1 RSV BCLK
STPCLK IGNNE
VSS D16 D19
D7 D30 VCC
VCC VREF2 D24
D13 D20 VSS
VSS D11 D3
D2 D14 VCC
VCC D18 D9
D12 D10 VSS
RSV D17 VREF3
D8 D5 VCC
VCC D1 D6
D4 D15 VSS
VSS BERR VREF4
D0 A34 VCC
BR1 RESET2 A32
RSV A26 VSS
VSS A29 A18
A27 A30 VCC
VCC A24 A23
A33 A20 VSS
VSS A31 VREF5
A17 A22 VCC
VCC A35 A25
EDGCTRL A19 VSS
VSS RESET A10 A5 A8 A4 BNR REQ1 REQ2 VTT RS1 VCC RS0 THERM
TRIP
SLP VCC VSS VCC
A21 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BSEL1 BSEL0 SMI VID3
VCC VSS A28 A3 A11 VREF6 A14 VTT REQ0 LOCK VREF7 AERR PWRGD RS2 RSV TMS VCC VSS
VSS VSS A15 A13 A9 AP0 VTT A7 REQ4 REQ3 VTT HITM HIT DBSY THRMDN THRMDP TCK VID0 VID2
RSV VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1
VSS A12 A16 A6 VTT AP1 VTT BPRI DEFER VTT RP TRDY DRDY BR0 ADS TRST TDI TDO
Pin Side View
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Z
Y
X
W
V
U
T
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
RSV
Datasheet 69
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Table 39. Signal Listing in Order by
Signal Name
Pin
No. Pin Name Signal Group
AK8 A3# AGTL+ I/O
AH12 A4# AGTL+ I/O
AH8 A5# AGTL+ I/O
AN9 A6# AGTL+ I/O
AL15 A7# AGTL+ I/O
AH10 A8# AGTL+ I/O
AL9 A9# AGTL+ I/O
AH6 A10# AGTL+ I/O
AK10 A11# AGTL+ I/O
AN5 A12# AGTL+ I/O
AL7 A13# AGTL+ I/O
AK14 A14# AGTL+ I/O
AL5 A15# AGTL+ I/O
AN7 A16# AGTL+ I/O
AE1 A17# AGTL+ I/O
Z6 A18# AGTL+ I/O
AG3 A19# AGTL+ I/O
AC3 A20# AGTL+ I/O
AE33 A20M# CMOS Input
AJ1 A21# AGTL+ I/O
AE3 A22# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB4 A24# AGTL+ I/O
AF6 A25# AGTL+ I/O
Y3 A26# AGTL+ I/O
AA1 A27# AGTL+ I/O
AK6 A28# AGTL+ I/O
Z4 A29# AGTL+ I/O
AA3 A30# AGTL+ I/O
AD4 A31# AGTL+ I/O
X6 A32# AGTL+ I/O
AC1 A33# AGTL+ I/O
W3 A34# AGTL+ I/O
AF4 A35# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AK24 AERR# AGTL+ I/O
AL11 AP0# AGTL+ I/O
AN13 AP1# AGTL+ I/O
W37 BCLK System Bus Clock
V4 BERR# AGTL+ I/O
B36 BINIT# AGTL+ I/O
AH14 BNR# AGTL+ I/O
G33 BP2# AGTL+ I/O
E37 BP3# AGTL+ I/O
C35 BPM0# AGTL+ I/O
E35 BPM1# AGTL+ I/O
AN17 BPRI# AGTL+ Input
AN29 BR0# AGTL+ I/O
X2 BR1#8 AGTL+ Input
AJ33 BSEL0 Power/Other
AJ31 BSEL1 Power/Other
Y33 CLKREF 7 Power/Other
C37 CPUPRES# Power/Other
W1 D0# AGTL+ I/O
T4 D1# AGTL+ I/O
N1 D2# AGTL+ I/O
M6 D3# AGTL+ I/O
U1 D4# AGTL+ I/O
S3 D5# AGTL+ I/O
T6 D6# AGTL+ I/O
J1 D7# AGTL+ I/O
S1 D8# AGTL+ I/O
P6 D9# AGTL+ I/O
Q3 D10# AGTL+ I/O
M4 D11# AGTL+ I/O
Q1 D12# AGTL+ I/O
L1 D13# AGTL+ I/O
N3 D14# AGTL+ I/O
U3 D15# AGTL+ I/O
H4 D16# AGTL+ I/O
R4 D17# AGTL+ I/O
P4 D18# AGTL+ I/O
H6 D19# AGTL+ I/O
L3 D20# AGTL+ I/O
G1 D21# AGTL+ I/O
F8 D22# AGTL+ I/O
G3 D23# AGTL+ I/O
K6 D24# AGTL+ I/O
E3 D25# AGTL+ I/O
E1 D26# AGTL+ I/O
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet 70
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
F12 D27# AGTL+ I/O
A5 D28# AGTL+ I/O
A3 D29# AGTL+ I/O
J3 D30# AGTL+ I/O
C5 D31# AGTL+ I/O
F6 D32# AGTL+ I/O
C1 D33# AGTL+ I/O
C7 D34# AGTL+ I/O
B2 D35# AGTL+ I/O
C9 D36# AGTL+ I/O
A9 D37# AGTL+ I/O
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
C15 D40# AGTL+ I/O
D14 D41# AGTL+ I/O
D12 D42# AGTL+ I/O
A7 D43# AGTL+ I/O
A11 D44# AGTL+ I/O
C11 D45# AGTL+ I/O
A21 D46# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
C13 D49# AGTL+ I/O
C25 D50# AGTL+ I/O
A13 D51# AGTL+ I/O
D16 D52# AGTL+ I/O
A23 D53# AGTL+ I/O
C21 D54# AGTL+ I/O
C19 D55# AGTL+ I/O
C27 D56# AGTL+ I/O
A19 D57# AGTL+ I/O
C23 D58# AGTL+ I/O
C17 D59# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
E25 D62# AGTL+ I/O
F16 D63# AGTL+ I/O
AL27 DBSY# AGTL+ I/O
AN19 DEFER# AGTL+ Input
C33 DEP0# AGTL+ I/O
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
C31 DEP1# AGTL+ I/O
A33 DEP2# AGTL+ I/O
A31 DEP3# AGTL+ I/O
E31 DEP4# AGTL+ I/O
C29 DEP5# AGTL+ I/O
E29 DEP6# AGTL+ I/O
A29 DEP7# AGTL+ I/O
AN27 DRDY# AGTL+ I/O
AG1 EDGCTRL 5 Power/Other
AC35 FERR# CMOS Output
AE37 FLUSH# CMOS Input
AM22 GND Power/Other
AM26 GND Power/Other
AM30 GND Power/Other
AM34 GND Power/Other
AM6 GND Power/Other
AN3 GND Power/Other
B12 GND Power/Other
B16 GND Power/Other
B20 GND Power/Other
B24 GND Power/Other
B28 GND Power/Other
B32 GND Power/Other
B4 GND Power/Other
B8 GND Power/Other
D18 GND Power/Other
D2 GND Power/Other
D22 GND Power/Other
D26 GND Power/Other
D30 GND Power/Other
D34 GND Power/Other
D4 GND Power/Other
E11 GND Power/Other
E15 GND Power/Other
E19 GND Power/Other
E7 GND Power/Other
F20 GND Power/Other
F24 GND Power/Other
F28 GND Power/Other
F32 GND Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet 71
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
F36 GND Power/Other
G5 GND Power/Other
H2 GND Power/Other
H34 GND Power/Other
K36 GND Power/Other
L5 GND Power/Other
M2 GND Power/Other
M34 GND Power/Other
P32 GND Power/Other
P36 GND Power/Other
A37 GND Power/Other
AB32 GND Power/Other
AC33 GND Power/Other
AC5 GND Power/Other
AD2 GND Power/Other
AD34 GND Power/Other
AF32 GND Power/Other
AF36 GND Power/Other
AG5 GND Power/Other
AH2 GND Power/Other
AH34 GND Power/Other
AJ11 GND Power/Other
AJ15 GND Power/Other
AJ19 GND Power/Other
AJ23 GND Power/Other
AJ27 GND Power/Other
AJ3 GND Power/Other
AJ7 GND Power/Other
AK36 GND Power/Other
AK4 GND Power/Other
AL1 GND Power/Other
AL3 GND Power/Other
AM10 GND Power/Other
AM14 GND Power/Other
AM18 GND Power/Other
Q5 GND Power/Other
R34 GND Power/Other
T32 GND Power/Other
T36 GND Power/Other
U5 GND Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
V2 GND Power/Other
V34 GND Power/Other
X32 GND Power/Other
X36 GND Power/Other
Y37 GND Power/Other
Y5 GND Power/Other
Z2 GND Power/Other
Z34 GND Power/Other
AL25 HIT# AGTL+ I/O
AL23 HITM# AGTL+ I/O
AE35 IERR# CMOS Output
AG37 IGNNE# CMOS Input
AG33 INIT# CMOS Input
M36 LINT0/INTR CMOS Input
L37 LINT1/NMI CMOS Input
AK20 LOCK# AGTL+ I/O
J33 PICCLK APIC Clock Input
J35 PICD0 APIC I/O
L35 PICD1 APIC I/O
W33 PLL1 Power/Other
U33 PLL2 Power/Other
A35 PRDY# AGTL+ Output
J37 PREQ# CMOS Input
AK26 PWRGOOD CMOS Input
AK18 REQ0# AGTL+ I/O
AH16 REQ1# AGTL+ I/O
AH18 REQ2# AGTL+ I/O
AL19 REQ3# AGTL+ I/O
AL17 REQ4# AGTL+ I/O
G37 Reserved Reserved for future use
L33 Reserved Reserved for future use
N33 Reserved Reserved for future use
N35 Reserved Reserved for future use
N37 Reserved Reserved for future use
Q33 Reserved Reserved for future use
Q35 Reserved Reserved for future use
Q37 Reserved Reserved for future use
R2 Reserved Reserved for future use
W35 Reserved Reserved for future use
Y1 Reserved Reserved for future use
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet 72
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
AK30 Reserved Reserved for future use
AM2 6 Reserved Reserved for future use
F10 Reserved Reserved for future use
X34 Reserved Reserved for future use
E21 Reserved11 Reserved for future use
X2 BR1#8 AGTL+ Input
AH4 RESET# 2 AGTL+ Input
X4 RESET2# 2 AGTL+ I/O
AN23 RP# AGTL+ I/O
AH26 RS0# AGTL + Input
AH22 RS1# AGTL+ Input
AK28 RS2# AGTL+ Input
AC37 RSP# AGTL+ Input
S35 RTTCTRL Power/Other
E27 SLEWCTRL Power/Other
AH30 SLP# CMOS Input
AJ35 SMI# CMOS Input
AG35 STPCLK# CMOS Input
AL33 TCK TAP Input
AN35 TDI TAP Input
AN37 TDO TAP Output
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AH28 THERMTRIP# CMOS Output
AK32 TMS TAP Input
AN25 TRDY# AGTL+ Input
AN33 TRST# TAP Input
AD36 VCC1.5
3 Power/Other
Z36 VCC2.5
1 Power/Other
AB36 VCCCMOS Power/Other
AA37 VCCCORE Power/Other
AA5 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB34 VCCCORE Power/Other
AD32 VCCCORE Power/Other
AE5 VCCCORE Power/Other
E5 VCCCORE Power/Other
E9 VCCCORE Power/Other
F14 VCCCORE Power/Other
F2 VCCCORE Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
F22 VCCCORE Power/Other
F26 VCCCORE Power/Other
F30 VCCCORE Power/Other
F34 VCCCORE Power/Other
F4 VCCCORE Power/Other
H32 VCCCORE Power/Other
H36 VCCCORE Power/Other
J5 VCCCORE Power/Other
K2 VCCCORE Power/Other
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
M32 VCCCORE Power/Other
N5 VCCCORE Power/Other
P2 VCCCORE Power/Other
P34 VCCCORE Power/Other
R32 VCCCORE Power/Other
R36 VCCCORE Power/Other
S5 VCCCORE Power/Other
T2 VCCCORE Power/Other
T34 VCCCORE Power/Other
V32 VCCCORE Power/Other
V36 VCCCORE Power/Other
W5 VCCCORE Power/Other
Y35 VCCCORE Power/Other
Z32 VCCCORE Power/Other
AF2 VCCCORE Power/Other
AF34 VCCCORE Power/Other
AH24 VCCCORE Power/Other
AH32 VCCCORE Power/Other
AH36 VCCCORE Power/Other
AJ13 VCCCORE Power/Other
AJ17 VCCCORE Power/Other
AJ21 VCCCORE Power/Other
AJ25 VCCCORE Power/Other
AJ29 VCCCORE Power/Other
AJ5 VCCCORE Power/Other
AK2 VCCCORE Power/Other
AK34 VCCCORE Power/Other
AM12 VCCCORE Power/Other
AM16 VCCCORE Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet 73
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
AM20 VCCCORE Power/Other
AM24 VCCCORE Power/Other
AM28 VCCCORE Power/Other
AM32 VCCCORE Power/Other
AM4 VCCCORE Power/Other
AM8 VCCCORE Power/Other
B10 VCCCORE Power/Other
B14 VCCCORE Power/Other
B18 VCCCORE Power/Other
B22 VCCCORE Power/Other
B26 VCCCORE Power/Other
B30 VCCCORE Power/Other
B34 VCCCORE Power/Other
B6 VCCCORE Power/Other
C3 VCCCORE Power/Other
D20 VCCCORE Power/Other
D24 VCCCORE Power/Other
D28 VCCCORE Power/Other
D32 VCCCORE Power/Other
D36 VCCCORE Power/Other
D6 VCCCORE Power/Other
E13 VCCCORE Power/Other
E17 VCCCORE Power/Other
AJ9 VCCCORE Power/Other
AL35 VID0 Power/Other
AM36 VID1 Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
AL37 VID2 Power/Other
AJ37 VID3 Power/Other
E33 VREF0 Power/Other
F18 VREF1 Power/Other
K4 VREF2 Power/Other
R6 VREF3 Power/Other
V6 VREF4 Power/Other
AD6 VREF5 Power/Other
AK12 VREF6 Power/Other
AK22 VREF7 Power/Other
AH20 VTT Power/Other
AK16 VTT Power/Other
AL13 VTT Power/Other
AL21 VTT Power/Other
AN11 VTT Power/Other
AN15 VTT Power/Other
G35 VTT Power/Other
AA33 VTT 4 Power/Other
AA35 VTT 4 Power/Other
AN21 VTT 4 Power/Other
E23 VTT 4 Power/Other
S33 VTT 4 Power/Other
S37 VTT 4 Power/Other
U35 VTT 4 Power/Other
U37 VTT 4 Power/Other
Table 39. Signal Listing in Order by
Signal Name (Continued)
Pin
No. Pin Name Signal Group
Datasheet 74
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Table 40. Signal Listing in Order by Pin
Number
Pin
No. Pin Name Signal Group
A3 D29# AGTL+ I/O
A5 D28# AGTL+ I/O
A7 D43# AGTL+ I/O
A9 D37# AGTL+ I/O
A11 D44# AGTL+ I/O
A13 D51# AGTL+ I/O
A15 D47# AGTL+ I/O
A17 D48# AGTL+ I/O
A19 D57# AGTL+ I/O
A21 D46# AGTL+ I/O
A23 D53# AGTL+ I/O
A25 D60# AGTL+ I/O
A27 D61# AGTL+ I/O
A29 DEP7# AGTL+ I/O
A31 DEP3# AGTL+ I/O
A33 DEP2# AGTL+ I/O
A35 PRDY# AGTL+ Output
A37 GND Power/Other
AA1 A27# AGTL+ I/O
AA3 A30# AGTL+ I/O
AA5 VCCCORE Power/Other
AA33 VTT 4 Power/Other
AA35 VTT 4 Power/Other
AA37 VCCCORE Power/Other
AB2 VCCCORE Power/Other
AB4 A24# AGTL+ I/O
AB6 A23# AGTL+ I/O
AB32 GND Power/Other
AB34 VCCCORE Power/Other
AB36 VCCCMOS Power/Other
AC1 A33# AGTL+ I/O
AC3 A20# AGTL+ I/O
AC5 GND Power/Other
AC33 GND Power/Other
AC35 FERR# CMOS Output
AC37 RSP# AGTL+ Input
AD2 GND Power/Other
AD4 A31# AGTL+ I/O
AD6 VREF5 Power/Other
AD32 VCCCORE Power/Other
AD34 GND Power/Other
AD36 VCC1.5
3 Power/Other
AE1 A17# AGTL+ I/O
AE3 A22# AGTL+ I/O
AE5 VCCCORE Power/Other
AE33 A20M# CMOS Input
AE35 IERR# CMOS Output
AE37 FLUSH# CMOS Input
AF2 VCCCORE Power/Other
AF4 A35# AGTL+ I/O
AF6 A25# AGTL+ I/O
AF32 GND Power/Other
AF34 VCCCORE Power/Other
AF36 GND Power/Other
AG1 EDGCTRL 5 Power/Other
AG3 A19# AGTL+ I/O
AG5 GND Power/Other
AG33 INIT# CMOS Input
AG35 STPCLK# CMOS Input
AG37 IGNNE# CMOS Input
AH2 GND Power/Other
AH4 RESET# 2 AGTL+ Input
AH6 A10# AGTL+ I/O
AH8 A5# AGTL+ I/O
AH10 A8# AGTL+ I/O
AH12 A4# AGTL+ I/O
AH14 BNR# AGTL+ I/O
AH16 REQ1# AGTL+ I/O
AH18 REQ2# AGTL+ I/O
AH20 VTT Power/Other
AH22 RS1# AGTL+ Input
AH24 VCCCORE Power/Other
AH26 RS0# AGTL + Input
AH28 THERMTRIP# CMOS Output
AH30 SLP# CMOS Input
AH32 VCCCORE Power/Other
AH34 GND Power/Other
AH36 VCCCORE Power/Other
AJ1 A21# AGTL+ I/O
AJ3 GND Power/Other
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet 75
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
AJ5 VCCCORE Power/Other
AJ7 GND Power/Other
AJ9 VCCCORE Power/Other
AJ11 GND Power/Other
AJ13 VCCCORE Power/Other
AJ15 GND Power/Other
AJ17 VCCCORE Power/Other
AJ19 GND Power/Other
AJ21 VCCCORE Power/Other
AJ23 GND Power/Other
AJ25 VCCCORE Power/Other
AJ27 GND Power/Other
AJ29 VCCCORE Power/Other
AJ31 BSEL1 Power/Other
AJ33 BSEL0 Power/Other
AJ35 SMI# CMOS Input
AJ37 VID3 Power/Other
AK2 VCCCORE Power/Other
AK4 GND Power/Other
AK6 A28# AGTL+ I/O
AK8 A3# AGTL+ I/O
AK10 A11# AGTL+ I/O
AK12 VREF6 Power/Other
AK14 A14# AGTL+ I/O
AK16 VTT Power/Other
AK18 REQ0# AGTL+ I/O
AK20 LOCK# AGTL+ I/O
AK22 VREF7 Power/Other
AK24 AERR# AGTL+ I/O
AK26 PWRGOOD CMOS Input
AK28 RS2# AGTL+ Input
AK30 Reserved Reserved for future use
AK32 TMS TAP Input
AK34 VCCCORE Power/Other
AK36 GND Power/Other
AL1 GND Power/Other
AL3 GND Power/Other
AL5 A15# AGTL+ I/O
AL7 A13# AGTL+ I/O
AL9 A9# AGTL+ I/O
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
AL11 AP0# AGTL+ I/O
AL13 VTT Power/Other
AL15 A7# AGTL+ I/O
AL17 REQ4# AGTL+ I/O
AL19 REQ3# AGTL+ I/O
AL21 VTT Power/Other
AL23 HITM# AGTL+ I/O
AL25 HIT# AGTL+ I/O
AL27 DBSY# AGTL+ I/O
AL29 THERMDN Power/Other
AL31 THERMDP Power/Other
AL33 TCK TAP Input
AL35 VID0 Power/Other
AL37 VID2 Power/Other
AM2 6 Reserved Reserved for future use
AM4 VCCCORE Power/Other
AM6 GND Power/Other
AM8 VCCCORE Power/Other
AM10 GND Power/Other
AM12 VCCCORE Power/Other
AM14 GND Power/Other
AM16 VCCCORE Power/Other
AM18 GND Power/Other
AM20 VCCCORE Power/Other
AM22 GND Power/Other
AM24 VCCCORE Power/Other
AM26 GND Power/Other
AM28 VCCCORE Power/Other
AM30 GND Power/Other
AM32 VCCCORE Power/Other
AM34 GND Power/Other
AM36 VID1 Power/Other
AN3 GND Power/Other
AN5 A12# AGTL+ I/O
AN7 A16# AGTL+ I/O
AN9 A6# AGTL+ I/O
AN11 VTT Power/Other
AN13 AP1# AGTL+ I/O
AN15 VTT Power/Other
AN17 BPRI# AGTL+ Input
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet 76
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
AN19 DEFER# AGTL+ Input
AN21 VTT 4 Power/Other
AN23 RP# AGTL+ I/O
AN25 TRDY# AGTL+ Input
AN27 DRDY# AGTL+ I/O
AN29 BR0# AGTL+ I/O
AN31 ADS# AGTL+ I/O
AN33 TRST# TAP Input
AN35 TDI TAP Input
AN37 TDO TAP Output
B2 D35# AGTL+ I/O
B4 GND Power/Other
B6 VCCCORE Power/Other
B8 GND Power/Other
B10 VCCCORE Power/Other
B12 GND Power/Other
B14 VCCCORE Power/Other
B16 GND Power/Other
B18 VCCCORE Power/Other
B20 GND Power/Other
B22 VCCCORE Power/Other
B24 GND Power/Other
B26 VCCCORE Power/Other
B28 GND Power/Other
B30 VCCCORE Power/Other
B32 GND Power/Other
B34 VCCCORE Power/Other
B36 BINIT# AGTL+ I/O
C1 D33# AGTL+ I/O
C3 VCCCORE Power/Other
C5 D31# AGTL+ I/O
C7 D34# AGTL+ I/O
C9 D36# AGTL+ I/O
C11 D45# AGTL+ I/O
C13 D49# AGTL+ I/O
C15 D40# AGTL+ I/O
C17 D59# AGTL+ I/O
C19 D55# AGTL+ I/O
C21 D54# AGTL+ I/O
C23 D58# AGTL+ I/O
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
C25 D50# AGTL+ I/O
C27 D56# AGTL+ I/O
C29 DEP5# AGTL+ I/O
C31 DEP1# AGTL+ I/O
C33 DEP0# AGTL+ I/O
C35 BPM0# AGTL+ I/O
C37 CPUPRES# Power/Other
D2 GND Power/Other
D4 GND Power/Other
D6 VCCCORE Power/Other
D8 D38# AGTL+ I/O
D10 D39# AGTL+ I/O
D12 D42# AGTL+ I/O
D14 D41# AGTL+ I/O
D16 D52# AGTL+ I/O
D18 GND Power/Other
D20 VCCCORE Power/Other
D22 GND Power/Other
D24 VCCCORE Power/Other
D26 GND Power/Other
D28 VCCCORE Power/Other
D30 GND Power/Other
D32 VCCCORE Power/Other
D34 GND Power/Other
D36 VCCCORE Power/Other
E1 D26# AGTL+ I/O
E3 D25# AGTL+ I/O
E5 VCCCORE Power/Other
E7 GND Power/Other
E9 VCCCORE Power/Other
E11 GND Power/Other
E13 VCCCORE Power/Other
E15 GND Power/Other
E17 VCCCORE Power/Other
E19 GND Power/Other
E21 Reserved11 Reserved for future use
E23 VTT 4 Power/Other
E25 D62# AGTL+ I/O
E27 SLEWCTRL Power/Other
E29 DEP6# AGTL+ I/O
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet 77
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
E31 DEP4# AGTL+ I/O
E33 VREF0 Power/Other
E35 BPM1# AGTL+ I/O
E37 BP3# AGTL+ I/O
F2 VCCCORE Power/Other
F4 VCCCORE Power/Other
F6 D32# AGTL+ I/O
F8 D22# AGTL+ I/O
F10 Reserved Reserved for future use
F12 D27# AGTL+ I/O
F14 VCCCORE Power/Other
F16 D63# AGTL+ I/O
F18 VREF1 Power/Other
F20 GND Power/Other
F22 VCCCORE Power/Other
F24 GND Power/Other
F26 VCCCORE Power/Other
F28 GND Power/Other
F30 VCCCORE Power/Other
F32 GND Power/Other
F34 VCCCORE Power/Other
F36 GND Power/Other
G1 D21# AGTL+ I/O
G3 D23# AGTL+ I/O
G5 GND Power/Other
G33 BP2# AGTL+ I/O
G35 VTT Power/Other
G37 Reserved Reserved for future use
H2 GND Power/Other
H4 D16# AGTL+ I/O
H6 D19# AGTL+ I/O
H32 VCCCORE Power/Other
H34 GND Power/Other
H36 VCCCORE Power/Other
J1 D7# AGTL+ I/O
J3 D30# AGTL+ I/O
J5 VCCCORE Power/Other
J33 PICCLK APIC Clock Input
J35 PICD0 APIC I/O
J37 PREQ# CMOS Input
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
K2 VCCCORE Power/Other
K4 VREF2 Power/Other
K6 D24# AGTL+ I/O
K32 VCCCORE Power/Other
K34 VCCCORE Power/Other
K36 GND Power/Other
L1 D13# AGTL+ I/O
L3 D20# AGTL+ I/O
L5 GND Power/Other
L33 Reserved Reserved for future use
L35 PICD1 APIC I/O
L37 LINT1/NMI CMOS Input
M2 GND Power/Other
M4 D11# AGTL+ I/O
M6 D3# AGTL+ I/O
M32 VCCCORE Power/Other
M34 GND Power/Other
M36 LINT0/INTR CMOS Input
N1 D2# AGTL+ I/O
N3 D14# AGTL+ I/O
N5 VCCCORE Power/Other
N33 Reserved Reserved for future use
N35 Reserved Reserved for future use
N37 Reserved Reserved for future use
P2 VCCCORE Power/Other
P4 D18# AGTL+ I/O
P6 D9# AGTL+ I/O
P32 GND Power/Other
P34 VCCCORE Power/Other
P36 GND Power/Other
Q1 D12# AGTL+ I/O
Q3 D10# AGTL+ I/O
Q5 GND Power/Other
Q33 Reserved Reserved for future use
Q35 Reserved Reserved for future use
Q37 Reserved Reserved for future use
R2 Reserved Reserved for future use
R4 D17# AGTL+ I/O
R6 VREF3 Power/Other
R32 VCCCORE Power/Other
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet 78
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES: See next page for notes.
R34 GND Power/Other
R36 VCCCORE Power/Other
S1 D8# AGTL+ I/O
S3 D5# AGTL+ I/O
S5 VCCCORE Power/Other
S33 VTT 4 Power/Other
S35 RTTCTRL Power/Other
S37 VTT 4 Power/Other
T2 VCCCORE Power/Other
T4 D1# AGTL+ I/O
T6 D6# AGTL+ I/O
T32 GND Power/Other
T34 VCCCORE Power/Other
T36 GND Power/Other
U1 D4# AGTL+ I/O
U3 D15# AGTL+ I/O
U5 GND Power/Other
U33 PLL2 Power/Other
U35 VTT 4 Power/Other
U37 VTT 4 Power/Other
V2 GND Power/Other
V4 BERR# AGTL+ I/O
V6 VREF4 Power/Other
V32 VCCCORE Power/Other
V34 GND Power/Other
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
V36 VCCCORE Power/Other
W1 D0# AGTL+ I/O
W3 A34# AGTL+ I/O
W5 VCCCORE Power/Other
W33 PLL1 Power/Other
W35 Reserved Reserved for future use
W37 BCLK System Bus Clock
X2 BR1#8 AGTL+ input
X4 RESET2# 2 AGTL+ I/O
X6 A32# AGTL+ I/O
X32 GND Power/Other
X34 Reserved Reserved for future use
X36 GND Power/Other
Y1 Reserved Reserved for future use
Y3 A26# AGTL+ I/O
Y5 GND Power/Other
Y33 CLKREF 7 Power/Other
Y35 VCCCORE Power/Other
Y37 GND Power/Other
Z2 GND Power/Other
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 VCCCORE Power/Other
Z34 GND Power/Other
Z36 VCC2.5
1 Power/Other
Table 40. Signal Listing in Order by Pin
Number (Continued)
Pin
No. Pin Name Signal Group
Datasheet 79
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. These pins are required for backwards compatibility with other Intel processors. They are not used by the
Pentium III processor. Refer to the appropriate platform design guide and Section 7.1 for implementation
details.
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
platform design guide and Section 7.1 for implementation details. If backwards compatibility is not required,
then RESET2# (X4) should be connected to GND.
3. VCC1.5V must be supplied by the same voltage source supplying the VTT pins.
4. These VTT pins must be left unconnected (N/C) for backwards compatibility with Celeron processors (CPUID
066xh). For designs which do not support the Celeron processors (CPUID 066xh), and for compatibility with
future processors, these VTT pins should be connected to the VTT plane. Refer to the appropriate platform
design guide and Section 7.1 for implementation details. For dual processor designs, these pins must be
connected to VTT.
5. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left
connected to VCCCORE. Refer to the appropriate platform design guide for implementation details.
6. Previously, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
(N/C).
7. Previously, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED. Refer to the Pentium® III
processor Specification Update for a complete listing of processors that support DP operation.
9. Future low voltage AGTL PGA370 designs will redefine this pin as VTT. Refer to the appropriate platform
design guide for connectivity and to the Pentium® III processor Specification Update for a complete listing of
processors that support the new pinout definition.
10.Future low voltage AGTL PGA370 designs define these pins as GND. Refer to the appropriate platform
design guide for connectivity and to the Pentium® III processor Specification Update for a complete listing of
processors that support the new pinout definition.
11.Future low voltage AGTL PGA370 designs define this pin as RESERVED and must be left unconnected.
Refer to the appropriate platform design guide for connectivity.
12.Future low voltage AGTL PGA370 designs will redefine these pins. Refer to the appropriate platform design
guide for connectivity and to the Pentium® III processor Specification Update for a complete listing of
processors that support the new pinout definition.
13.On AGTL and differential clock platforms, this pin is defined as BCLK#.
80 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
6.0 Boxed Processor Specifications
The Pentium III processor for the PGA370 socket is also offered as an Intel boxed processor. Intel
boxed processors are intended for system integrators who build systems from motherboards and
standard components. The boxed Pentium III processor for the PGA370 socket will be supplied
with an unattached fan heatsink. This section documents motherboard and system requirements for
the fan heatsink that will be supplied with the boxed Pentium III processor. This section is
particularly important for OEMs that manufacture motherboards for system integrators. Unless
otherwise noted, all figures in this section are dimensioned in inches.
Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These
dimensions should not be used as a generic keep-out zone for all heatsinks. It is the system
designer’s responsibility to consider their proprietary solution when designing to the required keepout
zone on their system platform and chassis. Refer to the Intel® Pentium® III Processor Thermal/
Mechanical Functional Specifications for further guidance. Contact your local Intel Sales
Representative for this document.
6.1 Mechanical Specifications for the Boxed Intel® Pentium® III
Processor
6.1.1 Boxed Processor Thermal Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed Pentium III processor fan
heatsink in the FC-PGA package. The boxed processor in the FC-PGA package ships with an unattached
fan heatsink. Figure 32 shows a mechanical representation of the boxed Pentium III
processor for the PGA370 socket in the Flip Chip Pin Grid Array (FC-PGA) package.
Section 5.3 of this document also shows the recommended mechanical keepout zones for the boxed
processor fan heatsink assembly. Figure 30 and Figure 31 show the required keepout dimensions
for the boxed processor thermal solution. The cooling fin orientation on the heatsink relative to the
PGA-370 socket is subject to change. Contact your local Intel Sales Representative for
documentation specific to the boxed fan heatsink orientation relative to the PGA-370 socket. Also,
contact your Intel representative for specific fan heatsink dimensions.
Figure 32. Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket
Datasheet 81
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The fan heatsink is designed to allow visibility of the FC-PGA processor markings located on top
of the package. The FC-PGA processor markings are visible after installation of the fan heatsink
due to notched sides of the heatsink base (see Figure 34). The boxed processor fan heatsink is also
asymmetrical in that the mechanical step feature (see Figure 33) must sit over the socket’s cam.
The step allows the heatsink to securely interface with the processor in order to meet thermal
requirements.
Note: The heatsink airflow keepout zones found in Figure 35 refer specifically to the boxed
processor’s active fan heatsink. This does not reflect the worst-case dimensions that may exist with
other third party passive or active fan heatsinks.
The Pentium III processor is manufactured in two different packages: FC-PGA and FC-PGA2. For
specifications on these two packages please see Section 5.0 of this document. Not all frequencies
of Pentium III processors are offered in both packages. The thermal solutions for these two
packages are incompatible. Therefore, the thermal solution shipped with each boxed Pentium III
processor should only be used with the accompanied processor.
Figure 33. Dimensions of Mechanical Step Feature in Heatsink Base
0.472
0.043
82 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
6.1.2 Boxed Processor Heatsink Weight
The boxed processor thermal cooling solution will not weigh more than 180 grams.
6.1.3 Boxed Processor Thermal Cooling Solution Clip
The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.
Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach
tabs in a way that interferes with the installation of the boxed processor thermal cooling solution
(see Section 5.3 for specification).
6.2 Thermal Specifications
This section describes the cooling requirements of the thermal cooling solution utilized by the
boxed processor.
6.2.1 Boxed Processor Cooling Requirements
The boxed processor is directly cooled with a fan heatsink. However, meeting the processor’s
temperature specification is also a function of the thermal design of the entire system, and
ultimately the responsibility of the system integrator. The processor temperature specification is
found in Section 4.0 of this document. The boxed processor fan heatsink is able to keep the
processor core within the specifications (see Table 33 and Table 34) in chassis that provide good
thermal management.
Figure 34. Dimensions of Notches in Heatsink Base
Datasheet 83
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of
the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and
decreases fan life. Figure 35 illustrates an acceptable airspace clearance for the fan heatsink. It is
also recommended that the air temperature entering the fan be kept below 45 ο C. Meeting the
processor’s temperature specification is the responsibility of the system integrator. The processor
temperature specification is found in Section 4.0 of this document.
6.3 Electrical Requirements for the Boxed Intel® Pentium® III
Processor
6.3.1 Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is attached
to the fan and will draw power from a power header on the motherboard. The power cable
connector and pinout are shown in Figure 36. Motherboards must provide a matched power header
to support the boxed processor. Table 41 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE (open-collector output) signal that
pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH to
match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE
signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard. Figure 37 shows the recommended location of the fan
power connector relative to the PGA370 socket. The motherboard power header should be
positioned within 4.00 inches (lateral) from the center of the PGA370 socket.
Figure 35. Thermal Airspace Requirement for all Boxed Intel® Pentium® III Processor Fan
Heatsinks in the PGA370 Socket
84 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 36. Boxed Processor Fan Heatsink Power Cable Connector Description
Table 41. Fan Heatsink Power and Signal Specifications
Description Min Typ Max
+12 V: 12 volt fan power supply 10.8 V 12 V 13.2 V
IC: Fan current draw 100 mA
SENSE: SENSE frequency (motherboard should pull this
pin up to appropriate VCC with resistor)
2 pulses per
fan revolution
Figure 37. Motherboard Power Header Placement Relative to the Boxed Intel® Pentium® III
Processor
Pin Signal
Straight square pin, 3-pin terminal housing with
polarizing ribs and friction locking ramp.
0.100" pin pitch, 0.025" square pin width.
Waldom/Molex P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,
or equivalent.
1
2
3
GND
+12V
SENSE
1 2 3
0.10"
Socket 7
0.10"
R = 4.00”
PGA370
Datasheet 85
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
7.0 Processor Signal Description
This section provides an alphabetical listing of all the Pentium III processor signals. The tables at
the end of this section summarize the signals by direction: output, input, and I/O.
7.1 Alphabetical Signals Reference
Table 42. Signal Description (Sheet 1 of 8)
Name Type Description
A[35:3]# I/O
The A[35:3]# (Address) signals define a 236-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
pins to determine their power-on configuration. See the Intel® Pentium® II
Processor Developer’s Manual for details.
A20M# I
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS# I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
AERR# I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
AP[1:0]# I/O
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the appropriate pins
of all processor system bus agents.
BCLK/BCLK# I
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
86 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
BERR# I/O
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without
a bus protocol violation. It may be driven by all processor system bus agents, and
must connect the appropriate pins of all such agents, if used. However, Pentium III
processors do not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
• Enabled or disabled.
• Asserted optionally for internal errors along with IERR#.
• Asserted optionally by the request initiator of a bus transaction after it observes
an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
BINIT# I/O
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not affected.
If BINIT# observation is disabled during power-on configuration, a central agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of
the system.
BNR# I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BP[3:2]# I/O The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BPM[1:0]# I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPRI# I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
Table 42. Signal Description (Sheet 2 of 8)
Name Type Description
Datasheet 87
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
BR0#
BR1#
I/O
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BSEL[1:0] I/O
These signals are used to select the system bus frequency. A BSEL[1:0] = “01”
selects a 100 MHz system bus frequency and a BSEL[1:0] = “11” selects a 133 MHz
system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the
same frequency. The Pentium III processor for the PGA370 socket operates at
100 MHz and 133 MHz system bus frequencies. Individual processors will only
operate at their specified front side bus (FSB) frequency. Either 100 MHz or
133 MHz, not both.
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 Mhz system bus frequency. 66 MHz operation is
not support by the Pentium III processor for the PGA370 socket; therefore, BSEL0 is
ignored.
These signals must be pulled up to 2.5 V or 3.3V with 1 KΩ resistors and provided
as a frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See Section 2.8.2 for
implementation examples.
CLKREF I
The CLKREF input is a filtered 1.25 V supply voltage for the processor PLL. A
voltage divider and decoupling solution is provided by the motherboard. See the
design guide for implementation details.
Table 42. Signal Description (Sheet 3 of 8)
Name Type Description
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate
bus signal protocol, as shown below.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal Agent 0 Pins Agent 1 Pins
BREQ0# BR0# BR1#
BREQ1# BR1# BR0#
BR[1:0]# Signal Agent IDs
Pin Sampled Active in RESET# Agent ID
BR0# 0
BR1# 3
88 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
CPUPRES# O
The CPUPRES# signal is defined to allow a system design to detect the presence of
a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[3:0]= 1111 (see Section 2.6), a system can determine if a socket
is occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.
D[63:0]# I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data
path between the processor system bus agents, and must connect the appropriate
pins on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
DBSY# I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
DEFER# I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEP[7:0]# I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DRDY# I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
EDGCTRL O
The EDGCTRL input adjusts the edge rate of AGTL+ output buffers for previous
processors and should be pulled up to VCCCORE with a 51 Ω ±5% resistor. See the
platform design guide for implementation details. This signal is not used by the
Pentium III processor.
FERR# O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel387™ coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
Table 42. Signal Description (Sheet 4 of 8)
Name Type Description
PGA370 Socket Occupation Truth Table
Signal Value Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0]
0
1111
Terminator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[3:0]
1
Any value PGA370 socket not occupied.
Datasheet 89
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
FLUSH# I
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to
determine its power-on configuration. See the P6 Family of Processors Hardware
Developer’s Manual for details.
HIT#
HITM#
I/O
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR# O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The processor
will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IGNNE# I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
INIT# I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must connect
the appropriate pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
LINT[1:0] I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
Table 42. Signal Description (Sheet 5 of 8)
Name Type Description
90 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
PICCLK I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICD[1:0] I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PLL1, PLL2 I
All Pentium III processors have an internal analog PLL clock generator that requires
a quiet power supply. PLL1 and PLL2 are inputs to this PLL and must be connected
to VCCCORE through a low pass filter that minimizes jitter. See the platform design
guide for implementation details.
PRDY# O The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ# I The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
PWRGOOD I
The PWRGOOD (Power Good) signal is processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies (VCCCORE,
etc.) are stable and within their specifications. Clean implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time that
the power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. The figure below illustrates the
relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width
specification in Table 19, and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
RESET# I
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCCCORE and
CLK have reached their proper specifications. On observing active RESET#, all
processor system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
P6 Family of Processors Hardware Developer’s Manual for details.
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor
system bus agents.
RESET2# I
The RESET2# pin is provided for compatibility with other Intel Architecture
processors. The Pentium III processor does not use the RESET2# pin. Refer to the
platform design guide for the proper connections of this signal.
RP# I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of all
processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
RS[2:0]# I
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
Table 42. Signal Description (Sheet 6 of 8)
Name Type Description
Datasheet 91
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
RSP# I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
RTTCTRL I
The RTTCTRL input signal provides AGTL+ termination control. The Pentium III
processor samples this input to sense the presence of motherboard AGTL+
termination. See the platform design guide for implementation details.
SLEWCTRL I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Pentium III
processor samples this input to determine the slew rate for AGTL+ signals when it is
the driving agent. See the platform design guide for implementation details.
SLP# I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SMI# I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK# I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
THERMDN O Thermal Diode Cathode. Used to calculate core (junction) temperature. See Section
4.3.
THERMDP I Thermal Diode Anode. Used to calculate core (junction) temperature. See Section
4.3.
THERMTRIP# O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will continue to
drive THERMTRIP# and remain stopped. The system designer should not act upon
THERMTRIP# until after RESET# input is de-asserted since, until this time, the
THERMTRIP# output is indeterminate.
TRDY# I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
Table 42. Signal Description (Sheet 7 of 8)
Name Type Description
92 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
7.2 Signal Summaries
Table 43 through Table 46 list attributes of the processor output, input, and I/O signals.
VID[3:0] O
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 2 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
VCOREDET O
The VCOREDET pin indicate the type of processor core present. This pin will float for
2.0 V VCCCORE based processor and will be shorted to VSS for the Pentium III
processor.
VCC1.5 I
The VCC1.5 V input pin provides the termination voltage for CMOS signals
interfacing to the processor. The Pentium III processor reroutes the 1.5 V input to
the VCCCMOS output via the package. The supply for VCC1.5 V must be the same one
used to supply VTT.
VCC2.5 I
The VCC2.5 V input pin provides the termination voltage for CMOS signals
interfacing to processors which require 2.5 V termination on the CMOS signals. This
signal is not used by the Pentium III processor.
VCCCMOS O The VccCMOS pin provides the CMOS voltage for use by the platform and is used
for terminating CMOS signals that interface to the processor.
VREF I
The VREF input pins supply the AGTL+ reference voltage, which is typically 2/3 of
VTT. VREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
logical 1.
Table 42. Signal Description (Sheet 8 of 8)
Name Type Description
Table 43. Output Signals
Name Active Level Clock Signal Group
CPUPRES# Low Asynch Power/Other
EDGCTRL N/A Asynch Power/Other
FERR# Low Asynch CMOS Output
IERR# Low Asynch CMOS Output
PRDY# Low BCLK AGTL+ Output
THERMTRIP# Low Asynch CMOS Output
VCOREDET N/A Asynch Power/Other
VID[3:0] N/A Asynch Power/Other
Table 44. Input Signals (Sheet 1 of 2)
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Input Always1
BCLK High — System Bus Clock Always
BPRI# Low BCLK AGTL+ Input Always
BR1# Low BCLK AGTL+ Input Always
Datasheet 93
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTE:
1. Synchronous assertion with active TDRY# ensures synchronization.
DEFER# Low BCLK AGTL+ Input Always
FLUSH# Low Asynch CMOS Input Always1
IGNNE# Low Asynch CMOS Input Always1
INIT# Low Asynch CMOS Input Always1
INTR High Asynch CMOS Input APIC disabled mode
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMOS Input Always
PWRGOOD High Asynch CMOS Input Always
RESET# Low BCLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RSP# Low BCLK AGTL+ Input Always
RTTCTRL N/A Asynch Power/Other
SLEWCTRL N/A Asynch Power/Other
SLP# Low Asynch CMOS Input During Stop-Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TRDY# Low BCLK AGTL+ Input
Table 44. Input Signals (Sheet 2 of 2)
Name Active Level Clock Signal Group Qualified
94 Datasheet
Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Table 45. Input/Output Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:3]# Low BCLK AGTL+ I/O ADS#, ADS#+1
ADS# Low BCLK AGTL+ I/O Always
AP[1:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
BP[3:2]# Low BCLK AGTL+ I/O Always
BPM[1:0]# Low BCLK AGTL+ I/O Always
BR0# Low BCLK AGTL+ I/O Always
BSEL[1:0] High Asynch Power/Other Always
D[63:0]# Low BCLK AGTL+ I/O DRDY#
DBSY# Low BCLK AGTL+ I/O Always
DEP[7:0]# Low BCLK AGTL+ I/O DRDY#
DRDY# Low BCLK AGTL+ I/O Always
LOCK# Low BCLK AGTL+ I/O Always
REQ[4:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
RP# Low BCLK AGTL+ I/O ADS#, ADS#+1
Table 46. Input/Output Signals (Multiple Driver)
Name Active Level Clock Signal Group Qualified
AERR# Low BCLK AGTL+ I/O ADS#+3
BERR# Low BCLK AGTL+ I/O Always
BINIT# Low BCLK AGTL+ I/O Always
BNR# Low BCLK AGTL+ I/O Always
HIT# Low BCLK AGTL+ I/O Always
HITM# Low BCLK AGTL+ I/O Always
PICD[1:0] High PICCLK APIC I/O Always